Inventor
Brian S. Lee
Inventor
Hsinchu, TW
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices23%
G11CStatic stores17%
H10DInorganic electric semiconductor devices15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
B82YSpecific uses or applications of nanostructures5%
H01FMagnets5%
H10NElectric solid-state devices not otherwise provided for5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
G01RMeasuring electric variables2%
PatentTitleYear
8,541,247'Non-volatile memory cell with lateral pinning'20138,537,587'Dual stage sensing for non-volatile memory'20138,508,981'Apparatus for variable resistive memory punchthrough access method'20138,487,390'Memory cell with stress-induced anisotropy'20138,289,748'Tuning a variable resistance of a resistive sense element'20128,289,759'Non-volatile memory cell with precessional switching'20128,203,865'Non-volatile memory cell with non-ohmic selection layer'20128,197,953'Magnetic stack design'20128,199,558'Apparatus for variable resistive memory punchthrough access method'20128,098,510'Variable resistive memory punchthrough access method'20128,050,072'Dual stage sensing for non-volatile memory'20118,050,092'NAND flash memory with integrated bit line capacitance'20117,961,497'Variable resistive memory punchthrough access method'20117,939,188'Magnetic stack design'20117,936,622'Defective bit scheme for multi-layer integrated memory device'20117,936,592'Non-volatile memory cell with precessional switching'20117,936,583'Variable resistive memory punchthrough access method'20117,936,585'Non-volatile memory cell with non-ohmic selection layer'20117,402,364'Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same'20087,329,916'DRAM cell arrangement with vertical MOS transistors'20087,087,947'Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same'20066,939,763'DRAM cell arrangement with vertical MOS transistors, and method for its fabrication'20056,828,615'Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices'20046,818,515'Method for fabricating semiconductor device with loop line pattern structure'20046,770,954'Semiconductor device with SI-GE layer-containing low resistance, tunable contact'20046,759,335'Buried strap formation method for sub-150 nm best DRAM devices'20046,737,316'Method of forming a deep trench DRAM cell'20046,703,279'Semiconductor device having contact of Si-Ge combined with cobalt silicide'20046,566,190'Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices'20036,562,714'Consolidation method of junction contact etch for below 150 nanometer deep trench-based DRAM devices'20036,544,888'Advanced contact integration scheme for deep-sub-150 nm devices'20036,528,367'Self-aligned active array along the length direction to form un-biased buried strap formation for sub-150 NM BEST DRAM devices'20036,521,956'Semiconductor device having contact of Si-Ge combined with cobalt silicide'20036,511,905'Semiconductor device with Si-Ge layer-containing low resistance, tunable contact'20036,475,859'Plasma doping for DRAM with deep trenches and hemispherical grains'20026,475,906'Gate contact etch sequence and plasma doping method for sub-150 NM DT-based DRAM devices'20026,472,302'Integration method for raised contact formation for sub-150 nm devices'20026,426,253'Method of forming a vertically oriented device in an integrated circuit'20026,372,567'Control of oxide thickness in vertical transistor structures'20026,362,040'Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates'20026,348,388'Process for fabricating a uniform gate oxide of a vertical transistor'20026,335,247'Integrated circuit vertical trench device and method of forming thereof'20026,284,666'Method of reducing RIE lag for deep trench silicon etching'20016,207,573'Differential trench open process'20016,159,874'Method of forming a hemispherical grained capacitor'20006,150,670'Process for fabricating a uniform gate oxide of a vertical transistor'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2002Based in New York, NY, US· patent location history
2002–2008Patents assigned to PROMOS TECHNOLOGIES INC (16)· patent assignee history
2002–2008Patents assigned to INFINEON TECHNOLOGIES AG (7)· patent assignee history
2002–2008Based in Hsinchu, TW· patent location history
2005–2008Based in Apple Valley, MN, US· patent location history
2011–2013Patents assigned to SEAGATE TECHNOLOGY LLC (18)· patent assignee history
2011–2013Based in Boston, MA, US· patent location history
2011–2013Based in Eden Prairie, MN, US· patent location history
2012–2013Patents assigned to LEE BRIAN (8)· patent assignee history
2012–2013Patents assigned to XI HAIWEN (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEAGATE TECHNOLOGY LLC | 18 | 2011–2013 |
| PROMOS TECHNOLOGIES INC | 16 | 2002–2008 |
| LEE BRIANself | 8 | 2012–2013 |
| INFINEON TECHNOLOGIES AG | 7 | 2002–2008 |
| XI HAIWEN | 5 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 15 | 2002–2008 |
| Boston, Massachusetts, US | 10 | 2011–2013 |
| New York, New York, US | 10 | 2000–2002 |
| Eden Prairie, Minnesota, US | 8 | 2011–2013 |
| Apple Valley, Minnesota, US | 2 | 2005–2008 |