Inventor
Peter Schrögmeier
Inventor
Munich, DE
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores67%
H03KPulse technique12%
G06FElectric digital data processing9%
G01RMeasuring electric variables3%
G10LSpeech analysis techniques or speech synthesis3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
7,751,231'Method and integrated circuit for determining the state of a resistivity changing memory cell'20107,363,561'Method and circuit arrangement for resetting an integrated circuit'20087,120,818'Method and device for data transfer'20067,058,840'Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock'20067,031,421'Method and device for initializing an asynchronous latch chain'20066,882,554'Integrated memory, and a method of operating an integrated memory'20056,847,581'Integrated circuit and method for operating the integrated circuit'20056,804,165'Latency time switch for an S-DRAM'20046,687,669'Method of reducing voice signal interference'20046,614,700'Circuit configuration with a memory array'20036,542,389'Voltage pump with switch-on control'20036,480,024'Circuit configuration for programming a delay in a signal path'20026,437,410'Integrated memory'20026,404,699'Integrated circuit having a command decoder'20026,401,224'Integrated circuit and method for testing it'20026,396,755'Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory'20026,388,944'Memory component with short access time'20026,385,123'Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated'20026,359,832'Method and circuit configuration for read-write mode control of a synchronous memory'20026,351,419'Integrated memory with a block writing function and global amplifiers requiring less space'20026,310,824'Integrated memory with two burst operation types'20016,285,605'Integrated memory having redundant units of memory cells, and test method for the redundant units'20016,275,445'Synchronous integrated memory'20016,272,035'Integrated memory'20016,256,219'Integrated memory having memory cells disposed at crossover points of word lines and bit lines'20016,188,642'Integrated memory having column decoder for addressing corresponding bit line'20016,144,590'Semiconductor memory having differential bit lines'20006,101,141'Integrated memory'20006,028,815'Integrated memory'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2001Patents assigned to SIEMENS AG (4)· patent assignee history
2000–2010Based in Munich, DE· patent location history
2001–2008Patents assigned to INFINEON TECHNOLOGIES AG (23)· patent assignee history
2002–2004Based in Mnchen, DE· patent location history
2004Based in Lindau, DE· patent location history
2005–2008Based in München, DE· patent location history
2010Patents assigned to QIMONDA AG (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 23 | 2001–2008 |
| SIEMENS AG | 4 | 2000–2001 |
| QIMONDA AG | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Munich, DE | 11 | 2000–2010 |
| Mnchen, DE | 11 | 2002–2004 |
| München, DE | 6 | 2005–2008 |
| Lindau, DE | 1 | 2004 |