Inventor

Gyu-Chul Kim

Inventor
Gyeonggi-do, KR

Overview

20→
Patents
1993–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices33%
H10BElectronic memory devices16%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
G11CStatic stores9%
H01LSemiconductor devices7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
G11BInformation storage based on relative movement between record carrier and transducer2%
PatentTitleYear
10,217,639Method of forming drain extended MOS transistors for high voltage circuits20199,799,401'Incremental step pulse programming'20179,673,195'Semiconductor device having sufficient process margin and method of forming same'20179,123,642'Method of forming drain extended MOS transistors for high voltage circuits'20158,193,047'Semiconductor device having sufficient process margin and method of forming same'20127,560,353'Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties'20097,221,031'Semiconductor device having sufficient process margin and method of forming same'20077,183,662'Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties'20077,112,856'Semiconductor device having a merged region and method of fabrication'20067,105,917'Semiconductor device having a fuse connected to a pad and fabrication method thereof'20066,759,748'Wiring structure of semiconductor device'20046,724,052'Semiconductor device and method of fabricating a semiconductor device'20046,399,987'MOS transistor having self-aligned well bias area'20026,355,515'Wiring structure of semiconductor device and method for manufacturing the same'20025,717,227'Bipolar junction transistors having insulated gate electrodes'19985,328,860'Method of manufacturing a semiconductor device'19945,323,379'Disk clamping apparatus including a clamp having a plurality of clamp jaws movable horizontally'19945,278,084'Method of manufacturing a semiconductor device'1994D0334738'Lap top computer'1993D0332944'Lap top computer'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (17)· patent assignee history
1994–1998Based in Seoul, KR· patent location history
2002–2006Based in Kyungki-do, KR· patent location history
2002–2004Based in Sungnam, KR· patent location history
2007–2012Based in Gyeonggi-do, KR· patent location history
2012Patents assigned to CHO HOO-SUNG (1)· patent assignee history
2012Patents assigned to JUNG SUNG-GON (1)· patent assignee history
2012Patents assigned to KIM GYU-CHUL (1)· patent assignee history
2015–2019Patents assigned to CYPRESS SEMICONDUCTOR CORP (2)· patent assignee history
2015–2019Based in Lakeville, MN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SAMSUNG ELECTRONICS CO LTD171993–2017
CYPRESS SEMICONDUCTOR CORP22015–2019
CHO HOO-SUNG12012
JUNG SUNG-GON12012
KIM GYU-CHULself12012
Locations
LocationPatentsSpan
Gyeonggi-do, KR42007–2012
Kyungki-do, KR42002–2006
Lakeville, Minnesota, US32015–2019
Seoul, KR31994–1998
Sungnam, KR22002–2004