Inventor

Joseph P. Bratt

Inventor

San Jose, CA, US

Overview

59→

Patents

1996–2020

Patent span

Physics

Primary field (CPC G)

Patents· 59 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing34%

G06TImage data processing or generation, in general29%

H04NPictorial communication, e.g. television17%

G09GArrangements or circuits for control of indicating devices using static means to present variable information11%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%

G06KGraphical data reading1%

H04LTransmission of digital information, e.g. telegraphic communication1%

PatentTitleYear

10,694,129Raw scaler with chromatic aberration correction2020 9,762,919'Chroma cache architecture in block processing pipelines'2017 9,741,099'Systems and methods for local tone mapping'2017 9,727,505'Clock control for DMA busses'2017 9,571,846'Data storage and access in block processing pipelines'2017 9,454,378'Global configuration broadcast'2016 9,336,563'Buffer underrun handling'2016 9,332,239'Systems and methods for RGB image processing'2016 9,262,798'Parameter FIFO'2016 9,229,894'Protocol conversion involving multiple virtual channels'2016 9,105,078'Systems and methods for local tone mapping'2015 9,077,943'Local image statistics collection'2015 9,032,113'Clock control for DMA busses'2015 9,025,867'Systems and methods for YCC image processing'2015 8,994,741'Streaming translation in display pipe'2015 8,917,336'Image signal processing involving geometric distortion correction'2014 8,872,946'Systems and methods for raw image processing'2014 8,773,457'Color space conversion'2014 8,749,568'Parameter FIFO'2014 8,749,565'Error check-only mode'2014 8,717,391'User interface pipe scalers with active regions'2014 8,711,170'Edge alphas for image translation'2014 8,711,173'Reproducible dither-noise injection'2014 8,681,976'System and method for device dependent and rate limited key generation'2014 8,675,004'Buffer underrun handling'2014 8,669,993'User interface unit for fetching only active regions of a frame'2014 8,533,513'Hardware-based power management of functional blocks'2013 8,525,895'Binning compensation filtering techniques for image signal processing'2013 8,508,612'Image signal processor line buffer configuration for processing ram image data'2013 8,508,621'Image sensor data formats and memory addressing techniques for image signal processing'2013 8,493,482'Dual image sensor image processing system and method'2013 8,405,668'Streaming translation in display pipe'2013 8,321,605'PIO interjection between beats of a DMA operation'2012 7,984,317'Hardware-based power management of functional blocks'2011 7,808,503'Deferred shading graphics pipeline processor having advanced features'2010 7,681,013'Method for variable length decoding using multiple configurable look-up tables'2010 7,653,776'Method and apparatus for selectively switching IC ports to card slots through the use of three switches per switch group'2010 7,558,947'Method and apparatus for computing vector absolute differences'2009 7,467,287'Method and apparatus for vector table look-up'2008 7,305,540'Method and apparatus for data processing'2007 7,167,181'Deferred shading graphics pipeline processor having advanced features'2007 7,114,058'Method and apparatus for forming and dispatching instruction groups based on priority comparisons'2006 7,055,018'Apparatus for parallel vector table look-up'2006 7,015,921'Method and apparatus for memory access'2006 6,877,020'Method and apparatus for matrix transposition'2005 6,848,032'Pipelining cache-coherence operations in a shared-memory multiprocessing system'2005 6,822,654'Memory controller chipset'2004 6,771,264'Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor'2004 6,717,576'Deferred shading graphics pipeline processor having advanced features'2004 6,697,076'Method and apparatus for address re-mapping'2004 6,693,639'Graphics processor with pipeline state storage and retrieval'2004 6,597,363'Graphics processor with deferred shading'2003 6,525,737'Graphics processor with pipeline state storage and retrieval'2003 6,268,875'Deferred shading graphics pipeline processor'2001 6,229,553'Deferred shading graphics pipeline processor'2001 5,740,402'Conflict resolution in interleaved memory systems with multiple parallel accesses'1998 5,632,025'Method for preventing multi-level cache system deadlock in a multi-processor system'1997 5,572,704'System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes'1996 5,537,538'Debug mode for a superscalar RISC processor'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2020Based in San Jose, CA, US· patent location history

2001–2007Patents assigned to APPLE COMPUTER (15)· patent assignee history

2007–2020Patents assigned to APPLE INC (40)· patent assignee history

2012–2016Patents assigned to BRATT JOSEPH P (23)· patent assignee history

2013–2016Patents assigned to COTE GUY (10)· patent assignee history

2013–2014Patents assigned to HOLLAND PETER F (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
APPLE INC	40	2007–2020
BRATT JOSEPH Pself	23	2012–2016
APPLE COMPUTER	15	2001–2007
COTE GUY	10	2013–2016
HOLLAND PETER F	9	2013–2014

Locations

Location	Patents	Span
San Jose, California, US	59	1996–2020