Inventor

Ralph N. Wall

Inventor
Beaverton, OR, US

Overview

19→
Patents
2005–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices23%
H01LSemiconductor devices20%
H03HImpedance networks, e.g. resonant circuits20%
Y10TTechnical subjects covered by former us classification13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
B23KSoldering or unsoldering3%
B81BMicrostructural devices or systems, e.g. micromechanical devices3%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems3%
H01CResistors3%
H02HEmergency protective circuit arrangements3%
PatentTitleYear
11,056,581Trench-gate insulated-gate bipolar transistors202110,727,326Trench-gate insulated-gate bipolar transistors (IGBTs)202010,546,948Electronic device including an insulated gate bipolar transistor having a field-stop region and a process of forming the same202010,388,726Accumulation enhanced insulated gate bipolar transistor (AEGT) and methods of use thereof201910,128,330Semiconductor device with a buried junction layer having an interspersed pattern of doped and counter-doped materials20189,564,424'ESD device and structure therefor'20179,337,178'Method of forming an ESD device and structure therefor'20169,111,758'Semiconductor component and method of manufacture'20158,952,768'Optimal acoustic impedance materials for polished substrate coating to suppress passband ripple in BAW resonators and filters'20158,522,411'Method to control BAW resonator top electrode edge during patterning'20138,512,800'Optimal acoustic impedance materials for polished substrate coating to suppress passband ripple in BAW resonators and filters'20138,201,311'Process of making a BAW resonator bi-layer top electrode'20127,960,200'Orientation-dependent etching of deposited AlN for structural use and sacrificial layers in MEMS'20117,737,612'BAW resonator bi-layer top electrode with zero etch undercut'20107,612,488'Method to control BAW resonator top electrode edge during patterning'20097,600,303'BAW resonator bi-layer top electrode with zero etch undercut'20097,567,024'Methods of contacting the top layer of a BAW resonator'20096,919,984'Metal trim mirror for optimized thin film resistor laser trimming'20056,855,585'Integrating multiple thin film resistors'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2011Patents assigned to MAXIM INTEGRATED PRODUCTS (7)· patent assignee history
2005–2015Based in Beaverton, OR, US· patent location history
2012–2015Patents assigned to TRIQUINT SEMICONDUCTOR INC (4)· patent assignee history
2012–2013Patents assigned to WALL RALPH N (3)· patent assignee history
2012–2013Patents assigned to BOUCHE GUILLAUME (2)· patent assignee history
2015–2021Based in Pocatello, ID, US· patent location history
2017–2021Patents assigned to SEMICONDUCTOR COMPONENTS IND LLC (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MAXIM INTEGRATED PRODUCTS72005–2011
SEMICONDUCTOR COMPONENTS IND LLC62017–2021
TRIQUINT SEMICONDUCTOR INC42012–2015
WALL RALPH Nself32012–2013
BOUCHE GUILLAUME22012–2013
Locations
LocationPatentsSpan
Beaverton, OR, US112005–2015
Pocatello, ID, US82015–2021