Inventor
Szu-Ping Tung
Inventor
Taipei, TW
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
C23CCoating metallic material3%
C23GCleaning or de-greasing of metallic material by chemical methods other than electrolysis3%
H10BElectronic memory devices3%
H10NElectric solid-state devices not otherwise provided for3%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
11,004,793Method of forming an interconnect structure having an air gap and structure thereof202111,004,734Metal-based etch-stop layer202110,867,794Patterning method for semiconductor devices and structures resulting therefrom202010,862,026Memory device202010,685,873Etch stop layer for semiconductor devices202010,535,816Via structure, MRAM device using the via structure and method for fabricating the MRAM device202010,468,297Metal-based etch-stop layer201910,340,223Method of forming an interconnect structure having an air gap and structure thereof201910,103,099Semiconductor devices and methods of forming same20189,917,058'Method of forming an interconnect structure having an air gap and structure thereof'20189,873,944Metal capping process and processing platform thereof20189,640,428'Self-aligned repairing process for barrier layer'20179,589,800'Method for integrated circuit patterning'20179,576,892'Semiconductor devices and methods of forming same'20179,543,198'Structure and method for forming interconnect structure'20179,514,928'Selective repairing process for barrier layer'20169,496,169'Method of forming an interconnect structure having an air gap and structure thereof'20169,487,864'Metal capping process and processing platform thereof'20169,324,606'Self-aligned repairing process for barrier layer'20169,218,986'Hard mask edge cover scheme'20159,129,814'Method for integrated circuit patterning'20158,980,745'Interconnect structures and methods of forming same'20158,940,635'Structure and method for forming interconnect structure'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (5)· patent assignee history
2015–2021Based in Taipei, TW· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (19)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 19 | 2016–2021 |
| TAIWAN SEMICONDUCTOR MFG | 5 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 23 | 2015–2021 |