Inventor

Peter Z. Onufryk

Inventor

Flanders, NJ, US

Overview

44→

Patents

1999–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing40%

H03MCoding21%

H04LTransmission of digital information, e.g. telegraphic communication15%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%

G11CStatic stores4%

H04MTelephonic communication4%

H04QSelecting3%

G05BControl or regulating systems in general1%

H01LSemiconductor devices1%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%

PatentTitleYear

10,410,975Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits2019 10,230,396Method and apparatus for layer-specific LDPC decoding2019 9,813,080'Layer specific LDPC decoder'2017 9,590,656'System and method for higher quality log likelihood ratios in LDPC decoding'2017 9,454,414'System and method for accumulating soft information in LDPC decoding'2016 9,448,881'Memory controller and integrated circuit device for correcting errors in data read from memory cells'2016 9,397,701'System and method for lifetime specific LDPC decoding'2016 9,235,467'System and method with reference voltage partitioning for low density parity check decoding'2016 9,146,890'Method and apparatus for mapped I/O routing in an interconnect switch'2015 9,128,858'Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values'2015 9,092,353'Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system'2015 9,025,495'Flexible routing engine for a PCI express switch and method of use'2015 8,995,302'Method and apparatus for translated routing in an interconnect switch'2015 8,990,661'Layer specific attenuation factor LDPC decoder'2015 8,707,122'Nonvolatile memory controller with two-stage error correction technique for enhanced reliability'2014 8,694,849'Shuffler error correction code system and method'2014 8,656,071'System and method for routing a data message through a message network'2014 8,656,257'Nonvolatile memory controller with concatenated error correction codes'2014 8,621,318'Nonvolatile memory controller with error detection for concatenated error correction codes'2013 8,601,346'System and method for generating parity data in a nonvolatile memory controller by using a distributed processing technique'2013 8,588,228'Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner'2013 8,554,968'Interrupt technique for a nonvolatile memory controller'2013 8,429,325'PCI express switch and method for multi-port non-transparent switching'2013 8,397,144'BCH data correction system and method'2013 8,170,007'Packet telephony appliance'2012 8,107,479'Method and system for telephony and high-speed data access on a broadband access network'2012 7,852,867'Integrated memory for storing egressing packet data, replay data and to-be egressed data'2010 7,827,555'Scheduler for a multiprocessing computing system'2010 7,773,591'Integrated memory for storing egressing packet data, replay data and to-be egressed data'2010 7,634,774'System and method of scheduling computing threads'2009 7,587,439'Method and apparatus for generating a random bit stream in true random number generator fashion'2009 7,478,186'Interrupt coalescer for DMA channel'2009 7,447,195'Packet telephony appliance'2008 7,386,774'Memory unit with controller managing memory access through JTAG and CPU interfaces'2008 7,353,345'External observation and control of data in a computing processor'2008 7,334,071'Expansion of cross-domain addressing for PCI-express packets passing through non-transparent bridge'2008 7,231,539'Reset circuit for resetting two clock domains'2007 7,167,997'Apparatus and method for limiting data transmission rates'2007 6,826,177'Packet telephony appliance'2004 6,707,819'Method and apparatus for the encapsulation of control information in a real-time data stream'2004 6,671,742'Method and apparatus for unifield control and data event exchange in a software system'2003 6,665,299'Method and system for telephony and high speed data access on a broadband access network'2003 6,498,797'Method and apparatus for communication services on a network'2002 5,909,369'Coordinating the states of a distributed finite state machine'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999Based in North Plainfield, NJ, US· patent location history

2002–2008Patents assigned to AT & T CORP (6)· patent assignee history

2002–2019Based in Flanders, NJ, US· patent location history

2007–2013Patents assigned to INTEGRATED DEVICE TECH (10)· patent assignee history

2012–2014Patents assigned to ONUFRYK PETER Z (12)· patent assignee history

2013–2016Patents assigned to PMC SIERRA US INC (14)· patent assignee history

2013–2014Patents assigned to MARELLI ALESSIA (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
PMC SIERRA US INC	14	2013–2016
ONUFRYK PETER Zself	12	2012–2014
INTEGRATED DEVICE TECH	10	2007–2013
AT & T CORP	6	2002–2008
MARELLI ALESSIA	5	2013–2014

Locations

Location	Patents	Span
Flanders, New Jersey, US	43	2002–2019
North Plainfield, New Jersey, US	1	1999