Inventor
Michael Mishaeli
Inventor
Zichron Yaakov, IL
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use25%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
H04LTransmission of digital information, e.g. telegraphic communication3%
G01RMeasuring electric variables2%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
PatentTitleYear
11,048,587Apparatus and method for detecting and recovering from data fetch errors202111,029,953Branch prediction unit in service of short microcode flows202111,023,233Methods, apparatus, and instructions for user level thread suspension202110,990,395System and method for communication using a register management array circuit202110,775,434System, apparatus and method for probeless field scan of a processor202010,678,623Error reporting and handling using a common error handler202010,656,697Processor core power event tracing202010,503,509System and method for communication using a register management array circuit201910,503,517Method for booting a heterogeneous system and presenting a symmetric core view201910,467,011Thread pause processors, methods, systems, and instructions201910,345,889Forcing a processor into a low power state201910,261,790Memory copy instructions, processors, methods, and systems201910,223,204Apparatus and method for detecting and recovering from data fetch errors201910,216,662Hardware mechanism for performing atomic actions on remote processors201910,185,566Migrating tasks between asymmetric computing elements of a multi-core processor201910,156,884Local power gate (LPG) interfaces for power-aware operations201810,127,039Extension of CPU context-state management for micro-architecture state20189,910,475'Processor core power event tracing'20189,898,330'Compacted context state management'20189,891,695'Flushing and restoring core memory content to external memory'20189,760,158'Forcing a processor into a low power state'20179,727,345'Method for booting a heterogeneous system and presenting a symmetric core view'20179,720,730'Providing an asymmetric multicore processor system transparently to an operating system'20179,684,541'Method and apparatus for determining thread execution parallelism'20179,660,799'Changing the clock frequency of a computing device'20179,519,324'Local power gate (LPG) interfaces for power-aware operations'20169,501,132'Instruction and logic for store broadcast and power management'20169,448,879'Apparatus and method for implement a multi-level memory hierarchy'20169,396,056'Conditional memory fault assist suppression'20169,361,101'Extension of CPU context-state management for micro-architecture state'20169,348,594'Core switching acceleration in asymmetric multiprocessor system'20169,250,901'Execution context swap between heterogeneous functional hardware units'20169,152,205'Mechanism for facilitating faster suspend/resume operations in computing systems'20159,058,201'Managing and tracking thread access to operating system extended features using map-tables containing location references and thread identifiers'20158,935,514'Optimizing performance of instructions based on sequence detection or information associated with the instructions'20158,909,988'Recoverable parity and residue error'20148,677,163'Context state management for processor feature sets'20148,631,261'Context state management for processor feature sets'20148,543,796'Optimizing performance of instructions based on sequence detection or information associated with the instructions'20137,558,946'Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2021Patents assigned to INTEL CORP (40)· patent assignee history
2009–2014Based in Zichron Yakov, IL· patent location history
2013–2019Patents assigned to MISHAELI MICHAEL (14)· patent assignee history
2013–2021Based in Zichron Yaakov, IL· patent location history
2015–2019Patents assigned to WEISSMANN ELIEZER (6)· patent assignee history
2015–2019Patents assigned to GINZBURG BORIS (5)· patent assignee history
2015–2019Patents assigned to NAVEH ALON (5)· patent assignee history
2015–2016Based in Zikhron-Yaakov, IL· patent location history
2017–2019Based in Haifa, IL· patent location history
2020Based in Yaakov, IL· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 40 | 2009–2021 |
| MISHAELI MICHAELself | 14 | 2013–2019 |
| WEISSMANN ELIEZER | 6 | 2015–2019 |
| GINZBURG BORIS | 5 | 2015–2019 |
| NAVEH ALON | 5 | 2015–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Zichron Yaakov, IL | 33 | 2013–2021 |
| Haifa, IL | 2 | 2017–2019 |
| Zikhron-Yaakov, IL | 2 | 2015–2016 |
| Zichron Yakov, IL | 2 | 2009–2014 |
| Yaakov, IL | 1 | 2020 |