Inventor
Koji Kuroki
Inventor
Tokyo, JP
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores42%
H03KPulse technique17%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses17%
H01LSemiconductor devices6%
H10BElectronic memory devices6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G06FElectric digital data processing3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
9,691,700'Semiconductor device including first and second dummy wirings'20179,633,980'Semiconductor device'2017RE045604'DLL circuit adapted to semiconductor device'20158,896,348'Semiconductor apparatus'20148,854,116'Semiconductor device'20148,710,861'Semiconductor device and method of adjusting characteristic thereof'20148,604,835'Semiconductor apparatus'20138,400,184'Semiconductor device and level shift circuit using the same'20138,120,978'Semiconductor memory device having auto-precharge function'20128,013,645'DLL circuit adapted to semiconductor device'20117,944,262'Duty correction circuit'20117,826,286'Semiconductor memory device with redundancy circuit'20107,755,366'Calibration circuit, semiconductor device including the same, and method of adjusting output characteristics of semiconductor device'20107,719,921'Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system'20107,710,172'DLL circuit, semiconductor memory device using the same, and data processing system'20107,681,062'Synchronous type semiconductor device for high speed data processing'20107,580,321'Synchronous semiconductor memory device'20097,391,662'Semiconductor memory device with redundancy circuit'20087,345,950'Synchronous semiconductor memory device'20087,317,344'Function selection circuit using a fuse option scheme'20087,254,070'Semiconductor memory device with redundancy circuit'20076,919,754'Fuse detection circuit'20056,751,128'Semiconductor memory device having shortened testing time'20046,128,209'Semiconductor memory device having dummy bit and word lines'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2008Patents assigned to OKI ELECTRIC IND CO LTD (6)· patent assignee history
2000–2017Based in Tokyo, JP· patent location history
2008–2014Patents assigned to ELPIDA MEMORY INC (13)· patent assignee history
2011Based in Chuo-ku, JP· patent location history
2012–2017Patents assigned to KUROKI KOJI (6)· patent assignee history
2014–2015Patents assigned to PS4 LUXCO SARL (3)· patent assignee history
2014Patents assigned to BAN YOKO (1)· patent assignee history
2017Based in Hachioji, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ELPIDA MEMORY INC | 13 | 2008–2014 |
| KUROKI KOJIself | 6 | 2012–2017 |
| OKI ELECTRIC IND CO LTD | 6 | 2000–2008 |
| PS4 LUXCO SARL | 3 | 2014–2015 |
| BAN YOKO | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 22 | 2000–2017 |
| Hachioji, JP | 1 | 2017 |
| Chuo-ku, JP | 1 | 2011 |