Inventor
Chin-Chi Teng
Inventor
Sunnyvale, CA, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
7,082,587'Method of estimating path delays in an IC'20067,051,310'Two-stage clock tree synthesis with buffer distribution balancing'20066,925,619'IC conductor capacitance estimation method'20056,782,519'Clock tree synthesis for mixed domain clocks'20046,763,513'Clock tree synthesizer for balancing reconvergent and crossover clock trees'20046,751,786'Clock tree synthesis for a hierarchically partitioned IC layout'20046,351,840'Method for balancing a clock tree'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002Patents assigned to SILICON PERSPECTIVE CORP (1)· patent assignee history
2002–2006Based in Sunnyvale, CA, US· patent location history
2004–2006Patents assigned to CADENCE DESIGN SYSTEMS INC (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 6 | 2004–2006 |
| SILICON PERSPECTIVE CORP | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 7 | 2002–2006 |