Inventor

Gregg B. Lesartre

Inventor

Fort Collins, CO, US

Overview

92→

Patents

1997–2021

Patent span

Physics

Primary field (CPC G)

Patents· 92 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing60%

H04LTransmission of digital information, e.g. telegraphic communication13%

G11CStatic stores11%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%

H03MCoding3%

H01LSemiconductor devices2%

H10BElectronic memory devices2%

A61BDiagnosis1%

E02DFoundations1%

G01RMeasuring electric variables1%

PatentTitleYear

11,126,372External memory controller2021 11,119,780Side cache2021 11,086,797Systems and methods for restricting write access to non-volatile memory2021 11,016,683Serializing access to fault tolerant memory2021 10,983,865Adjusting memory parameters2021 10,972,394Network congestion management2021 10,922,178Masterless raid for byte-addressable non-volatile memory2021 10,824,465Transaction request epochs2020 10,817,361Controlling error propagation due to fault in computing node of a distributed computing system2020 10,802,936Memory location remapping and wear-levelling2020 10,789,115Transmitter that does not resend a packet despite receipt of a message to resend the packet2020 10,735,030Re-encoding data associated with failed memory devices2020 10,693,811Age class based arbitration2020 10,671,291Iterative write sequence interrupt2020 10,664,410Transmitting contents of an operation field to a media controller2020 10,657,016Recovering stranded data2020 10,620,861Retrieve data block from determined devices2020 10,540,109Serializing access to fault tolerant memory2020 10,497,441Determining first write strength2019 10,491,545Virtual channel routing2019 10,474,389Write tracking for memories2019 10,474,380External memory controller2019 10,460,800Data sensing in crosspoint memory structures2019 10,452,498Fault tolerance for persistent main memory2019 10,452,567Non-volatile memory to store resettable data2019 10,437,500Committing altered metadata to a non-volatile storage device2019 10,417,091Memory device having error correction logic2019 10,402,113Live migration of data2019 10,355,978Calculating times to live for transaction requests2019 10,318,767Multi-tier security framework2019 10,318,205Managing data using a number of non-volatile memory arrays2019 10,312,943Error correction code in memory2019 10,303,622Data write to subset of memory devices2019 10,275,307Detection of error patterns in memory dies2019 10,254,988Memory device write based on mapping2019 10,248,571Saving position of a wear level rotation2019 10,241,715Rendering data invalid in a memory array2019 10,235,078Meta-data block within a non-volatile memory device2019 10,191,884Managing a multi-lane serial link2019 10,176,043Memory controller2019 10,152,399Recovering stranded data2018 9,972,379First data in response to second read request2018 9,946,656Completion packet return based on eviction or flush2018 9,927,988'Data move engine to move a block of data'2018 9,773,547'Non-volatile memory with multiple latency tiers'2017 9,742,403'State-retaining logic cell'2017 9,721,656'Encoded cross-point array'2017 9,575,898'Implementing coherency with reflective memory'2017 9,146,848'Link training for a serdes link'2015 9,053,072'End node transactions at threshold-partial fullness of storage space'2015 8,732,331'Managing latencies in a multiprocessor interconnect'2014 8,370,478'Testing a data communication architecture'2013 8,225,048'Systems and methods for resource access'2012 8,000,322'Crossbar switch debugging'2011 7,992,058'Method and apparatus for loopback self testing'2011 7,903,556'Method of controlling data transfers between nodes in a computer system'2011 7,721,159'Passing debug information'2010 7,672,222'Link failures'2010 7,624,213'Passing identification information'2009 7,613,958'Error detection in a system having coupled channels'2009 7,606,253'Successful transactions'2009 7,461,321'Error detection'2008 7,454,514'Processing data with uncertain arrival time'2008 7,444,681'Security measures in a partitionable computing system'2008 7,436,777'Failed link training'2008 7,363,402'Data communications architecture employing parallel SERDES channels'2008 7,310,762'Detection of errors'2007 7,178,015'Security measures in a partitionable computing system'2007 6,857,036'Hardware method for implementing atomic semaphore operations using code macros'2005 6,643,766'Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor'2003 6,542,965'Cache line replacement using cable status to bias way selection'2003 6,408,363'Speculative pre-flush of data in an out-of-order execution processor system'2002 6,405,287'Cache line replacement using cache status to bias way selection'2002 6,131,156'Optimized storage system and method for a processor that executes instructions out of order'2000 6,003,107'Circuitry for providing external access to signals that are internal to an integrated circuit chip package'1999 5,956,477'Method for processing information in a microprocessor to facilitate debug and performance monitoring'1999 5,881,224'Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle'1999 5,880,671'Flexible circuitry and method for detecting signal patterns on a bus'1999 5,875,340'Optimized storage system and method for a processor that executes instructions out of order'1999 5,867,644'System and method for on-chip debug support and performance monitoring in a microprocessor'1999 5,838,944'System for storing processor register data after a mispredicted branch'1998 5,838,942'Panic trap system and method'1998 5,809,275'Store-to-load hazard resolution system and method for a processor that executes instructions out of order'1998 5,799,167'Instruction nullification system and method for a processor that executes instructions out of order'1998 5,796,997'Fast nullify system and method for transforming a nullify function into a select function'1998 5,796,975'Operand dependency tracking system and method for a processor that executes instructions out of order'1998 5,784,587'Method and system for recovering from cache misses'1998 5,761,474'Operand dependency tracking system and method for a processor that executes instructions out of order'1998 5,761,713'Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank'1998 5,758,178'Miss tracking system and method'1998 5,748,934'Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words'1998 5,644,609'Apparatus and method for reading and writing remote registers on an integrated circuit chip using a minimum of interconnects'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2003Patents assigned to HEWLETT PACKARD CO (22)· patent assignee history

1997–2021Based in Fort Collins, CO, US· patent location history

2003–2019Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (29)· patent assignee history

2012–2015Patents assigned to LESARTRE GREGG B (3)· patent assignee history

2012–2014Patents assigned to BOCKHAUS JOHN W (2)· patent assignee history

2017–2021Patents assigned to HEWLETT PACKARD ENTPR DEV LP (48)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HEWLETT PACKARD ENTPR DEV LP	48	2017–2021
HEWLETT PACKARD DEVELOPMENT CO	29	2003–2019
HEWLETT PACKARD CO	22	1997–2003
LESARTRE GREGG Bself	3	2012–2015
BOCKHAUS JOHN W	2	2012–2014

Locations

Location	Patents	Span
Fort Collins, CO, US	92	1997–2021