Inventor
Satoshi Isa
Inventor
Tokyo, JP
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1040%
G11CStatic stores18%
H01LSemiconductor devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
G06FElectric digital data processing6%
H05KPrinted circuits6%
H10BElectronic memory devices3%
H10DInorganic electric semiconductor devices3%
H03FAmplifiers1%
H03KPulse technique1%
PatentTitleYear
11,081,468Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses202110,600,762Apparatuses comprising semiconductor dies in face-to-face arrangements202010,431,566Apparatuses comprising semiconductor dies in face-to-face arrangements201910,115,709Apparatuses comprising semiconductor dies in face-to-face arrangements20189,589,921'Semiconductor device'20179,418,967'Semiconductor device'20169,159,663'Semiconductor device with respective electrode pad rows and respective external electrodes electrically connected and arranged in the respective end portions of the substrate'20158,970,052'Semiconductor device stack with bonding layer and wire retaining member'20158,796,077'Semiconductor device'20148,604,601'Semiconductor device having wiring layers with power-supply plane and ground plane'20138,587,097'Semiconductor device that suppresses malfunctions due to noise generated in internal circuit'20138,581,417'Semiconductor device stack with bonding layer and wire retaining member'20138,569,898'Semiconductor device'20138,426,983'Semiconductor device'20138,331,182'Semiconductor device including plural electrode pads'20128,243,465'Semiconductor device with additional power supply paths'20128,063,476'Semiconductor device'20117,956,470'Semiconductor device'20117,944,026'Semiconductor device'20117,875,986'Semiconductor device'20117,847,377'Semiconductor device including semiconductor chip with two pad rows'20107,823,096'Inductance analysis system and method and program therefor'20107,816,768'Semiconductor device including ground and power-supply planes and a dielectric layer between the ground and power-supply planes'20107,777,350'Semiconductor stack package having wiring extension part which has hole for wiring'20107,694,245'Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor'20107,689,944'Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package'20107,681,154'Method for designing device, system for aiding to design device, and computer program product therefor'20107,667,317'Semiconductor package with bypass capacitor'20107,642,635'Stacked semiconductor package'20107,569,428'Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same'20097,538,431'Semiconductor device'20097,391,113'Semiconductor device'20087,239,169'Semiconductor apparatus capable of preventing occurrence of multiple reflection, driving method, and setting method thereof'20076,977,832'Semiconductor memory device capable of improving quality of voltage waveform given in a signal interconnection layer'20056,175,527'Semiconductor memory device having reduced component count and lower wiring density'20016,094,381'Semiconductor memory device with redundancy circuit'20006,075,749'Semiconductor memory device'20006,067,271'Semiconductor memory device and a driving method of the same'20005,995,432'Semiconductor memory device having N-channel MOS transistor for pulling up PMOS sources of sense amplifiers'19995,986,943'Semiconductor memory device for shortening the set up time and hold time of control signals in synchronous DRAM'19995,798,973'Semiconductor memory device having redundant memory cells'19985,703,824'Semiconductor memory device'19975,677,882'Semiconductor memory having redundancy memory decoder circuit'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2001Patents assigned to NEC CORP (9)· patent assignee history
1997–2021Based in Tokyo, JP· patent location history
2005–2014Patents assigned to ELPIDA MEMORY INC (24)· patent assignee history
2011–2017Patents assigned to ISA SATOSHI (10)· patent assignee history
2011–2017Patents assigned to KATAGIRI MITSUAKI (9)· patent assignee history
2014–2017Patents assigned to PS4 LUXCO SARL (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ELPIDA MEMORY INC | 24 | 2005–2014 |
| ISA SATOSHIself | 10 | 2011–2017 |
| KATAGIRI MITSUAKI | 9 | 2011–2017 |
| NEC CORP | 9 | 1997–2001 |
| PS4 LUXCO SARL | 5 | 2014–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 43 | 1997–2021 |