Inventor
Kiichiro Mukai
Inventor
Hachioji, JP
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10BElectronic memory devices12%
H10DInorganic electric semiconductor devices12%
C23CCoating metallic material6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H01JElectric discharge tubes or discharge lamps4%
B05BSpraying apparatus2%
B05CApparatus for applying fluent materials to surfaces, in general2%
C23FNon-mechanical removal of metallic material from surface2%
PatentTitleYear
6,747,339'Integrated circuit having reduced soft errors and reduced penetration of alkali impurities into the substrate'20046,551,765'Coating apparatus, discharge device, and coating method'20035,643,473'Dry etching method'19975,391,915'Integrated circuit having reduced soft errors and reduced penetration of alkali impurities into the substrate'19955,292,673'Method of manufacturing a semiconductor device'19945,147,500'Dry etching method'19925,079,191'Process for producing a semiconductor device'19925,013,526'Superconducting alloys comprising tungsten, molybdenum, silicon and oxygen'19914,956,043'Dry etching apparatus'19904,943,344'Etching method'19904,937,650'Semiconductor capacitor device with dual dielectric'19904,926,238'Semiconductor device and method for producing the same'19904,897,709'Titanium nitride film in contact hole with large aspect ratio'19904,891,684'Semiconductor device'19904,857,137'Process for surface treatment'19894,842,891'Method of forming a copper film by chemical vapor deposition'19894,809,052'Semiconductor memory device'19894,636,833'Semiconductor device'19874,599,135'Thin film deposition'19864,570,175'Three-dimensional semiconductor device with thin film monocrystalline member contacting substrate at a plurality of locations'19864,365,264'Semiconductor device with high density low temperature deposited Si.sub.w N.sub.x H.sub.y O.sub.z passivating layer'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1982–2004Patents assigned to HITACHI LTD (20)· patent assignee history
1982–2004Based in Hachioji, JP· patent location history
1990–1994Based in Tokyo, JP· patent location history
2003Patents assigned to TOSHIBA KK (1)· patent assignee history
2003Based in Yokohama, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 20 | 1982–2004 |
| TOSHIBA KK | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hachioji, JP | 17 | 1982–2004 |
| Tokyo, JP | 3 | 1990–1994 |
| Yokohama, JP | 1 | 2003 |