Inventor

Chih Chieh Yeh

Inventor
Taipei, TW

Overview

168→
Patents
2003–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 168 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices21%
G11CStatic stores15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H10BElectronic memory devices7%
B82YSpecific uses or applications of nanostructures3%
H10HInorganic light-emitting semiconductor devices having potential barriers0%
A61KPreparations for medical, dental or toiletry purposes0%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations0%
PatentTitleYear
10,872,893Dual nitride stressor for semiconductor device and method of manufacturing202010,867,841Semiconductor device and method of manufacturing the same202010,825,907Self-aligned contact and manufacturing method thereof202010,811,318FIN field effect transistor (FinFET) device structure with dummy FIN structure202010,804,268Vertical gate semiconductor device with steep subthreshold slope202010,804,367Gate stacks for stack-fin channel I/O devices and nanowire channel core devices202010,804,375Semiconductor device and method for manufacturing the same202010,727,110Semiconductor device and method of manufacturing the same202010,727,344Method of manufacturing a semiconductor device with multilayered channel structure202010,727,298Strained nanowire CMOS device and method of forming202010,720,496FinFET structures and methods of forming the same202010,700,206Semiconductor device and manufacturing method thereof202010,693,003Integrated circuit transistor structure with high germanium concentration SiGe stressor202010,672,667Semiconductor device and method202010,665,569Vertical transistor device and method for fabricating the same202010,535,732Strained nanowire CMOS device and method of forming202010,522,409Fin field effect transistor (FinFET) device structure with dummy fin structure and method for forming the same201910,522,625Multi-gate device and method of fabrication thereof201910,522,694Methods of manufacturing semiconductor device201910,516,056Semiconductor device and manufacturing method thereof201910,504,796Semiconductor device and method for manufacturing the same201910,483,262Dual nitride stressor for semiconductor device and method of manufacturing201910,483,157Semiconductor device and method of manufacturing the same201910,438,851Threshold voltage adjustment for a gate-all-around semiconductor structure201910,374,059Structure and formation method of semiconductor device structure with nanowires201910,355,133Method for forming a semiconductor device including a stacked wire structure201910,340,366Semiconductor device and manufacturing method thereof201910,297,508Semiconductor device and method201910,290,550Strain enhancement for FinFETs201910,290,546Threshold voltage adjustment for a gate-all-around semiconductor structure201910,269,800Vertical gate semiconductor device with steep subthreshold slope201910,269,934Method for manufacturing tunnel field effect transistor201910,263,091Multiple gate field effect transistors having oxygen-scavenged gate stack201910,204,985Structure and formation method of semiconductor device structure201910,181,524Vertical transistor device and method for fabricating the same201910,170,374Semiconductor device and method for manufacturing the same201910,164,032Self-aligned contact and manufacturing method thereof201810,147,819Semiconductor device and manufacturing method thereof201810,141,310Short channel effect suppression201810,134,847FinFET structures and methods of forming the same201810,134,843Multi-gate device and method of fabrication thereof201810,134,640Semiconductor device structure with semiconductor wire201810,062,782Method of manufacturing a semiconductor device with multilayered channel structure201810,037,912Semiconductor device and method of manufacturing the same201810,038,080Semiconductor device and manufacturing method thereof201810,002,969Semiconductor device and manufacturing method thereof20189,997,616Semiconductor device having a strained region20189,972,545System and method for a field-effect transistor with dual vertical gates20189,887,100'Methods of forming semiconductor devices and structures thereof'20189,876,117Structure and formation method of semiconductor device structure20189,853,101Strained nanowire CMOS device and method of forming20179,741,829'Semiconductor device and manufacturing method thereof'20179,735,274'Semiconductor device including a stacked wire structure'20179,728,461'Method of forming semiconductor device with different threshold voltages'20179,721,829'FinFETs with different fin height and EPI height setting'20179,711,412'FinFETs with different fin heights'20179,698,060'Germanium FinFETs with metal gates and stressors'20179,659,826'Asymmetric source/drain depths'20179,660,025'Structure and formation method of semiconductor device structure'20179,660,082'Integrated circuit transistor structure with high germanium concentration SiGe stressor'20179,659,780'Multiple gate field-effect transistors having oxygen-scavenged gate stack'20179,660,033'Multi-gate device and method of fabrication thereof'20179,647,071'FINFET structures and methods of forming the same'20179,640,441'Voids in STI regions for forming bulk FinFETs'20179,627,540'Semiconductor device and manufacturing method thereof'20179,627,531'Field-effect transistor with dual vertical gates'20179,601,598'Method of manufacturing a fin-like field effect transistor (FinFET) device'20179,583,399'Semiconductor device and manufacturing method thereof'20179,577,071'Method of making a strained structure of a semiconductor device'20179,564,489'Multiple gate field-effect transistors having oxygen-scavenged gate stack'20179,515,071'Asymmetric source/drain depths'20169,502,409'Multi-gate semiconductor devices'20169,466,678'Semiconductor device and manufacturing method thereof'20169,461,041'Metal gate finFET device'20169,450,094'Semiconductor process and fin-shaped field effect transistor'20169,425,102'FinFETs with different fin heights'20169,419,134'Strain enhancement for FinFETs'20169,397,097'Gate structure for semiconductor device'20169,385,046'Voids in STI regions for forming bulk FinFETs'20169,349,652'Method of forming semiconductor device with different threshold voltages'20169,263,342'Semiconductor device having a strained region'20169,257,344'FinFETs with different fin height and EPI height setting'20169,245,805'Germanium FinFETs with metal gates and stressors'20169,177,801'FinFET device having a strained region'20159,171,929'Strained structure of semiconductor device and method of making the strained structure'20159,112,052'Voids in STI regions for forming bulk FinFETs'20159,087,725'FinFETs with different fin height and EPI height setting'20158,987,824'Multi-gate semiconductor devices'20158,941,153'FinFETs with different fin heights'20158,921,218'Metal gate finFET device and method of fabricating thereof'20148,896,055'Accumulation type FinFET, circuits and fabrication method thereof'20148,847,293'Gate structure for semiconductor device'20148,796,759'Fin-like field effect transistor (FinFET) device and method of manufacturing same'20148,748,993'FinFETs with multiple fin heights'20148,673,709'FinFETs with multiple fin heights'20148,653,609'FinFET design with reduced current crowding'20148,653,608'FinFET design with reduced current crowding'20148,623,728'Method for forming high germanium concentration SiGe stressor'20148,501,591'Method for manufacturing a multiple-bit-per-cell memory'20138,482,057'Circuit and method for a three dimensional non-volatile memory'20138,445,340'Sacrificial offset protection film for a FinFET device'20138,373,238'FinFETs with multiple Fin heights'20138,369,140'Systems and methods for programming a memory device'20138,264,032'Accumulation type FinFET, circuits and fabrication method thereof'20128,264,021'Finfets and methods for forming the same'20128,223,553'Systems and methods for programming a memory device'20127,888,707'Gated diode nonvolatile memory process'20117,804,152'Recessed shallow trench isolation'20107,710,774'NAND type multi-bit charge storage memory array and methods for operating and fabricating the same'20107,672,157'Gated diode nonvolatile memory cell array'20107,529,128'Integrated code and data flash memory'20097,514,742'Recessed shallow trench isolation'20097,486,568'Method and apparatus for protection from over-erasing nonvolatile memory cells'20097,485,530'Method for manufacturing a multiple-gate charge trapping non-volatile memory'20097,483,307'Method and apparatus for sensing in charge trapping non-volatile memory'20097,474,558'Gated diode nonvolatile memory cell array'20097,439,085'Method and apparatus for electroluminescence'20087,440,328'Operation methods for a non-volatile memory cell in an array'20087,414,888'Program method and circuit of non-volatile memory'20087,397,701'Method and apparatus for operating a string of charge trapping memory cells'20087,387,932'Method for manufacturing a multiple-gate charge trapping non-volatile memory'20087,366,024'Method and apparatus for operating a string of charge trapping memory cells'20087,345,920'Method and apparatus for sensing in charge trapping non-volatile memory'20087,327,607'Method and apparatus for operating nonvolatile memory cells in a series arrangement'20087,327,611'Method and apparatus for operating charge trapping nonvolatile memory'20087,324,376'Method and apparatus for operating nonvolatile memory cells in a series arrangement'20087,321,145'Method and apparatus for operating nonvolatile memory cells with modified band structure'20087,307,888'Method and apparatus for operating nonvolatile memory in a parallel arrangement'20077,283,389'Gated diode nonvolatile memory cell array'20077,272,043'Operation methods for a non-volatile memory cell in an array'20077,272,038'Method for operating gated diode nonvolatile memory cell'20077,269,062'Gated diode nonvolatile memory cell'20077,230,277'Method and apparatus for electroluminescence'20077,224,619'Method and apparatus for protection from over-erasing nonvolatile memory cells'20077,209,386'Charge trapping non-volatile memory and method for gate-by-gate erase for same'20077,180,123'Method for programming programmable eraseless memory'20077,173,849'Method of programming and erasing multi-level flash memory'20077,170,785'Method and apparatus for operating a string of charge trapping memory cells'20077,158,411'Integrated code and data flash memory'20077,132,350'Method for manufacturing a programmable eraseless memory'20067,133,317'Method and apparatus for programming nonvolatile memory'20067,130,215'Method and apparatus for operating a non-volatile memory device'20067,120,059'Memory array including multiple-gate charge trapping non-volatile cells'20067,106,625'Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same'20067,095,544'Micromirror and products using the same'20067,072,220'Method and apparatus for operating a non-volatile memory array'20067,072,219'Method and apparatus for operating a non-volatile memory array'20067,057,938'Nonvolatile memory cell and operating method'20067,035,147'Overerase protection of memory cells for nonvolatile memory'20067,031,196'Nonvolatile semiconductor memory and operating method of the memory'20066,996,011'NAND-type non-volatile memory cell and method for operating same'20066,970,380'Method for programming non-volatile memory'20056,958,934'Method of programming and erasing multi-level flash memory'20056,917,073'ONO flash memory array for improving a disturbance between adjacent memory cells'20056,914,819'Non-volatile flash memory'20056,882,575'Erasing method for non-volatile memory'20056,829,175'Erasing method for non-volatile memory'20046,822,910'Non-volatile memory and operating method thereof'20046,801,453'Method and apparatus of a read scheme for non-volatile memory'20046,785,163'Trim circuit and method for tuning a current level of a reference cell in a flash memory'20046,721,204'Memory erase method and device with optimal data retention for nonvolatile memory'20046,690,601'Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same'20046,687,160'Reference current generation circuit for multiple bit flash memory'20046,665,212'Reference current generating circuit of multiple bit flash memory'20036,657,894'Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells'20036,646,924'Non-volatile memory and operating method thereof'20036,643,176'Reference current generation circuit for multiple bit flash memory'20036,614,694'Erase scheme for non-volatile memory'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2013Patents assigned to MACRONIX INT CO LTD (63)· patent assignee history
2003–2020Based in Taipei, TW· patent location history
2004–2017Based in Hsinchu, TW· patent location history
2006–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (26)· patent assignee history
2006–2008Based in Jhongshan District, TW· patent location history
2006Based in Jhongshan, TW· patent location history
2012–2016Patents assigned to YEH CHIH CHIEH (17)· patent assignee history
2013–2016Patents assigned to LEE TSUNG-LIN (7)· patent assignee history
2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (76)· patent assignee history
2016Based in Tainan, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD762015–2020
MACRONIX INT CO LTD632003–2013
TAIWAN SEMICONDUCTOR MFG262006–2016
YEH CHIH CHIEHself172012–2016
LEE TSUNG-LIN72013–2016
Locations
LocationPatentsSpan
Taipei, TW1492003–2020
Hsinchu, TW112004–2017
Jhongshan District, TW52006–2008
Tainan, TW22016
Jhongshan, TW12006