Inventor
VEERARAGHAVAN S. BASKER
Inventor
US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H01LSemiconductor devices27%
B82YSpecific uses or applications of nanostructures17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10BElectronic memory devices1%
PatentTitleYear
12,598,759High-density metal-insulator-metal capacitor integration wth nanosheet stack technology202612,563,817Integrating gate-cuts and single diffusion break isolation post-RMG using low-temperature protective liners202612,482,742Enhanced linerless vias202512,477,779Gate-all-around field-effect-transistor with wrap-around-channel inner spacer202512,464,813Semiconductor device having hybrid middle of line contacts202512,438,034Narrowing single diffusion break202512,432,960Wraparound contact with reduced distance to channel202512,417,944Formation of trench silicide source or drain contacts without gate damage202512,414,328Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors202512,376,369FinFET devices202512,324,184Replacement gate cross-couple for static random-access memory scaling202512,317,555Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor202512,310,054Late replacement bottom isolation for nanosheet devices202512,255,204Vertical FET replacement gate formation with variable fin pitch202512,224,312Field effect transistors with bottom dielectric isolation202512,119,341Electrostatic discharge diode having dielectric isolation layer202412,119,393Punch through stopper in bulk finFET device202412,100,746Gate-all-around field effect transistor with bottom dielectric isolation202412,100,744Wrap around contact process margin improvement with early contact cut202412,087,691Semiconductor structures with backside gate contacts202412,009,435Integrated nanosheet field effect transistors and floating gate memory cells202411,990,508Dual step etch-back inner spacer formation202411,955,526Thick gate oxide device option for nanosheet device202411,894,361Co-integrated logic, electrostatic discharge, and well contact devices on a substrate202411,894,436Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages202411,757,012Source and drain contact cut last process to enable wrap-around-contact202311,710,768Hybrid diffusion break with EUV gate patterning202311,695,057Protective bilayer inner spacer for nanosheet devices202311,688,741Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering202311,646,306Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate202311,621,332Wraparound contact to a buried power rail202311,615,988FinFET devices202311,443,982Formation of trench silicide source or drain contacts without gate damage202211,404,560Punch through stopper in bulk finFET device202211,387,319Nanosheet transistor device with bottom isolation202211,380,589Selective removal of semiconductor fins202211,355,401Field effect transistor202211,349,029Structure to enable titanium contact liner on pFET source/drain regions202211,348,999Nanosheet semiconductor devices with sigma shaped inner spacer202211,227,923Wrap around contact process margin improvement with early contact cut202211,201,242Structure to enable titanium contact liner on pFET source/drain regions202111,189,693Transistor having reduced contact resistance202111,152,464Self-aligned isolation for nanosheet transistor202111,145,551FinFET devices202111,139,385Interface-less contacts to source/drain regions and gate electrode over active portion of device202111,139,372Dual step etch-back inner spacer formation2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to IBM (39)· patent assignee history
2021–2022Patents assigned to TESSERA INC (2)· patent assignee history
2021–2026Based in US· patent location history
2022–2023Patents assigned to TESSERA LLC (3)· patent assignee history
2024–2025Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (2)· patent assignee history
2026Patents assigned to INT BUSINESS MACHINES CORPORATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 39 | 2021–2026 |
| TESSERA LLC | 3 | 2022–2023 |
| ADEIA SEMICONDUCTOR SOLUTIONS LLC | 2 | 2024–2025 |
| TESSERA INC | 2 | 2021–2022 |
| INT BUSINESS MACHINES CORPORATION | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 46 | 2021–2026 |