Inventor
Blair D. Milburn
Inventor
Beaverton, OR, US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
5,758,058'Apparatus and method for initializing a master/checker fault detecting microprocessor'19985,687,371'Selection from a plurality of bus operating speeds for a processor bus interface during processor reset'19975,524,233'Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations'19965,050,068'Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991Patents assigned to UNIV DUKE (1)· patent assignee history
1991–1998Based in Beaverton, OR, US· patent location history
1996–1998Patents assigned to INTEL CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 3 | 1996–1998 |
| UNIV DUKE | 1 | 1991 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 4 | 1991–1998 |