Inventor
JUN ZHAI
Inventor
US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices6%
H05KPrinted circuits4%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
H01GCapacitors2%
H10BElectronic memory devices2%
A01GHorticulture1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
12,588,494Die stitching and harvesting of arrayed structures202612,550,412Structure and method for fabricating a computing system with an integrated voltage regulator module202612,506,117Wafer level integration of passive devices202512,469,765Thermally enhanced chip-on-wafer or wafer-on-wafer bonding202512,456,692Microelectronic package RDL patterns to reduce stress in RDLs across components202512,451,436Interconnecting a plurality of dies having spare input/output circuit202512,368,137High bandwidth die to die interconnect with package area reduction202512,322,730Wafer reconstitution and die-stitching202512,283,549High density interconnection using fanout interposer chiplet202512,261,132Structure and method for sealing a silicon IC202512,249,599Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring202512,159,835High density 3D interconnect configuration202412,134,870Fluctuation zone state slope protection system that responds to hydrological changes202412,119,275Recessed lid and ring designs and lid local peripheral reinforcement designs202412,087,689Selectable monolithic or external scalable die-to-die interconnection system methodology202412,074,077Flexible package architecture concept in fanout202412,068,324Multi-die fine grain integrated voltage regulation202412,033,982Fully interconnected heterogeneous multi-layer reconstructed silicon device202412,021,035Interconnecting dies by stitch routing202411,967,528Structure and method for fabricating a computing system with an integrated voltage regulator module202411,966,977Guarantee fund calculation with allocation for self-referencing risk202411,908,819Semiconductor packaging substrate fine pitch metal bump and reinforcement structures202411,862,557Selectable monolithic or external scalable die-to-die interconnection system methodology202411,824,015Structure and method for sealing a silicon IC202311,749,631Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability202311,735,526High density 3D interconnect configuration202311,735,567Wafer reconstitution and die-stitching202311,728,266Die stitching and harvesting of arrayed structures202311,699,949Power management system switched capacitor voltage regulator with integrated passive device202311,670,548Structure and method for fabricating a computing system with an integrated voltage regulator module202311,646,302Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring202311,625,786Guarantee fund calculation with allocation for self-referencing risk202311,594,494High density interconnection using fanout interposer chiplet202311,587,909High bandwidth die to die interconnect with package area reduction202311,561,144Wearable electronic device with fluid-based pressure sensing202311,545,455Semiconductor packaging substrate fine pitch metal bump and reinforcement structures202311,532,563Package integration using fanout cavity substrate202211,515,261Multiple component integration in fanout package with different back side metallization and thicknesses202211,476,203Die-to-die routing through a seal ring202211,404,337Scalable extreme large size substrate integration202211,398,456Wafer level integration of passive devices202211,317,573Modular vertical water storage greening system202211,309,246High density 3D interconnect configuration202211,217,563Fully interconnected heterogeneous multi-layer reconstructed silicon device202211,182,857Guarantee fund calculation with allocation for self-referencing risk202111,158,621Double side mounted large MCM package with memory channel length reduction202111,158,607Wafer reconstitution and die-stitching2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to APPLE INC (42)· patent assignee history
2021–2024Patents assigned to CHICAGO MERCANTILE EXCHANGE INC (3)· patent assignee history
2021–2026Based in US· patent location history
2022–2024Patents assigned to UNIV SOOCHOW (2)· patent assignee history
2022–2024Based in CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLE INC | 42 | 2021–2026 |
| CHICAGO MERCANTILE EXCHANGE INC | 3 | 2021–2024 |
| UNIV SOOCHOW | 2 | 2022–2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 45 | 2021–2026 |
| CN | 2 | 2022–2024 |