Inventor
Chun-Yi Yang
Inventor
Hsinchu, TW
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices23%
H01LSemiconductor devices18%
H10DInorganic electric semiconductor devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
F21YIndexing scheme associated with subclasses f21k, f21l, f21s and f21v, relating to the form or the kind of the light sources or of the colour of the light emitted5%
G06FElectric digital data processing5%
F21SNon-portable lighting devices3%
F21VFunctional features or details of lighting devices or systems thereof3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
G05FSystems for regulating electric or magnetic variables3%
PatentTitleYear
11,079,083Rotating lighting decoration202110,840,371Ultra high voltage semiconductor device with electrostatic discharge capabilities202010,804,231Passivation scheme for pad openings and trenches202010,558,779Method of redistribution layer routing for 2.5-dimensional integrated circuit packages202010,461,183Ultra high voltage semiconductor device with electrostatic discharge capabilities201910,334,669LED arrangement and LED driving method201910,312,207Passivation scheme for pad openings and trenches20199,928,334'Redistribution layer routing for integrated fan-out wafer-level chip-scale packages'20189,882,046'Ultra high voltage semiconductor device with electrostatic discharge capabilities'20189,608,060'Isolation structure for semiconductor device'20179,312,348'Ultra high voltage semiconductor device with electrostatic discharge capabilities'20167,838,947'Read-only memory device coded with selectively insulated gate electrodes'20107,192,811'Read-only memory device coded with selectively insulated gate electrodes'20076,849,526'Method of improving device resistance'20056,821,684'Method for fabricating mask ROM with self-aligned coding'20046,794,253'Mask ROM structure and method of fabricating the same'20046,720,629'Structure of a memory device with buried bit line'20046,649,526'Method for implanting and coding a read-only memory with automatic alignment at four corners'20036,468,869'Method of fabricating mask read only memory'20026,440,803'Method of fabricating a mask ROM with raised bit-line on each buried bit-line'20026,397,377'Method of performing optical proximity corrections of a photo mask pattern by using a computer'20026,166,943'Method of forming a binary code of a ROM'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2010Patents assigned to MACRONIX INT CO LTD (11)· patent assignee history
2000–2018Based in Hsinchu County, TW· patent location history
2002–2003Based in Chu-Tong, TW· patent location history
2005–2020Based in Hsinchu, TW· patent location history
2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history
2017–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (6)· patent assignee history
2018–2020Patents assigned to ANAGLOBE TECH INC (2)· patent assignee history
2019Patents assigned to SIGNIFY HOLDING BV (1)· patent assignee history
2019Based in Shanghai, CN· patent location history
2021Based in Tainan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MACRONIX INT CO LTD | 11 | 2000–2010 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 6 | 2017–2020 |
| ANAGLOBE TECH INC | 2 | 2018–2020 |
| SIGNIFY HOLDING BV | 1 | 2019 |
| TAIWAN SEMICONDUCTOR MFG | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 11 | 2005–2020 |
| Hsinchu County, TW | 6 | 2000–2018 |
| Chu-Tong, TW | 3 | 2002–2003 |
| Tainan, TW | 1 | 2021 |
| Shanghai, CN | 1 | 2019 |