LexDanaLexDanabeta
Inventor

Rakesh Kumar Sinha

Inventor
Edison, NJ, US

Overview

51→
Patents
2002–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication31%
G11CStatic stores17%
G06FElectric digital data processing12%
H04QSelecting12%
H04JMultiplex communication11%
H04WWireless communication networks7%
B62DMotor vehicles1%
G06NComputing arrangements based on specific computational models1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H01LSemiconductor devices1%
PatentTitleYear
10,826,976Model-driven implementation of services on a software-defined network202010,733,013Information-technology workflows using executable tiles distributed between workflow instances202010,732,947Information-technology workflow using tiles that declaratively specify datatypes202010,732,934Information-technology workflows using executable tiles202010,693,575System and method for throughput prediction for cellular networks202010,614,865Boost generation circuitry for memory202010,601,731Broadcast services platform and methods for use therewith202010,469,567Model-driven implementation of services on a software-defined network201910,447,616Broadcast services platform and methods for use therewith201910,432,342Routing and regenerator planning in a carrier's core reconfigurable optical network201910,397,123Method and system for managing service quality according to network status predictions201910,171,197Method and apparatus for routing traffic using asymmetrical optical connections201910,147,483Robust write driver scheme for static random access memory compilers201810,140,044Efficient memory bank design20189,947,419Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits20189,928,889'Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories'20189,880,837'Artifact manager for release automation'20189,875,776Bit writability implementation for memories20189,875,790Boost charge recycle for low-power memory20189,837,144Apparatus and method for controlling boost capacitance for low power memory circuits20179,756,112'Method and system for managing service quality according to network status predictions'20179,735,912'Method and apparatus for routing traffic using asymmetrical optical connections'20179,712,604'Customized configuration of cloud-based applications prior to deployment'20179,652,211'Policy management of deployment plans'20179,639,691'Dynamic database and API-accessible credentials data store'20179,413,640'Method and apparatus for routing traffic using asymmetrical optical connections'20169,278,720'Aerodynamic drag reducing apparatus'20169,246,623'Method and apparatus for routing traffic using asymmetrical optical connections'20169,111,589'Memory timing circuit'20159,030,863'Read/write assist for memories'20158,929,153'Memory with multiple word line design'20158,817,605'Cross-layer reconfiguration method for surviving multiple-link network failures'20148,761,601'1:N sparing of router resources at geographically dispersed locations'20148,693,267'Signal synchronization in multi-voltage domains'20148,441,874'Memory device with robust write assist'20138,411,518'Memory device with boost compensation'20138,406,622'1:N sparing of router resources at geographically dispersed locations'20138,243,586'Cross-layer reconfiguration method for surviving multiple-link network failures'20128,068,412'Link selection schemes for avoiding channel contention'20118,010,694'Network performance and reliability evaluation taking into account multiple traffic matrices'20117,974,213'Methods and apparatus to select composite link cost-out thresholds'20117,916,657'Network performance and reliability evaluation taking into account abstract components'20117,567,511'Method and apparatus for computing the cost of providing VPN service'20097,551,550'Method and system for allocating protection path resources'20097,450,516'Link selection schemes for avoiding channel contention'20087,254,141'Method, system and storage medium for allocating bandwidth in a communication network'20076,985,445'Generation of test suites for interoperability of reactive communication systems'20066,904,462'Method and system for allocating protection path resources'20056,728,214'Testing of network routers under given routing protocols'20046,697,335'Quality of service routing in information networks over paths having performance-dependent costs'20046,412,054'Storage disk declustering method'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2006Based in Manville, NJ, US· patent location history
2005–2009Based in Eatontown, NJ, US· patent location history
2008–2020Based in Edison, NJ, US· patent location history
2009–2011Patents assigned to AT & T IP II LP (4)· patent assignee history
2011–2020Patents assigned to AT & T IP I LP (17)· patent assignee history
2012–2014Patents assigned to SINHA RAKESH KUMAR (6)· patent assignee history
2015–2020Patents assigned to QUALCOMM INC (11)· patent assignee history
2015–2020Based in Bangalore, IN· patent location history
2017–2020Patents assigned to VMWARE INC (7)· patent assignee history
2017–2020Based in Sunnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
AT & T IP I LP172011–2020
QUALCOMM INC112015–2020
VMWARE INC72017–2020
SINHA RAKESH KUMARself62012–2014
AT & T IP II LP42009–2011
Locations
LocationPatentsSpan
Edison, New Jersey, US222008–2020
Bangalore, IN112015–2020
Sunnyvale, California, US62017–2020
Eatontown, New Jersey, US32005–2009
Manville, New Jersey, US32002–2006