Inventor
Kamel Benaissa
Inventor
Dallas, TX, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices42%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H01LSemiconductor devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G06FElectric digital data processing4%
H02JElectric power networks4%
H10BElectronic memory devices4%
G11CStatic stores2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
10,128,145Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells20189,966,373MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts20189,583,609'MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts'20179,543,374'Low temperature coefficient resistor in CMOS flow'20179,508,708'Poly resistor for metal gate integrated circuits'20168,940,598'Low temperature coefficient resistor in CMOS flow'20158,940,612'Poly resistor for metal gate integrated circuits'20158,753,941'High performance asymmetric cascoded transistor'20148,716,827'Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells'20148,609,483'Method of building compensated isolated P-well devices'20138,604,543'Compensated isolated p-well DENMOS devices'20138,405,154'Low cost transistors using gate orientation and optimized implants'20138,294,243'Lateral bipolar transistor with compensated well regions'20128,232,158'Compensated isolated p-well DENMOS devices'20128,134,204'DEMOS transistors with STI and compensated well in drain'20128,114,729'Differential poly doping and circuits therefrom'20127,994,009'Low cost transistors using gate orientation and optimized implants'20117,829,405'Lateral bipolar transistor with compensated well regions'20107,053,465'Semiconductor varactor with reduced parasitic resistance'20066,847,095'Variable reactor (varactor) with engineered capacitance-voltage characteristics'20056,548,337'Method of manufacturing a high gain bipolar junction transistor with counterdoped base in CMOS technology'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2018Patents assigned to TEXAS INSTRUMENTS INC (20)· patent assignee history
2003–2006Based in Richardson, TX, US· patent location history
2005–2013Based in Dallas, TX, US· patent location history
2011–2015Patents assigned to BENAISSA KAMEL (10)· patent assignee history
2011–2013Patents assigned to BALDWIN GREG C (6)· patent assignee history
2011–2013Patents assigned to EKBOTE SHASHANK S (2)· patent assignee history
2012–2013Patents assigned to KAMATH ANANTH (2)· patent assignee history
2014–2018Based in Garland, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 20 | 2003–2018 |
| BENAISSA KAMELself | 10 | 2011–2015 |
| BALDWIN GREG C | 6 | 2011–2013 |
| EKBOTE SHASHANK S | 2 | 2011–2013 |
| KAMATH ANANTH | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dallas, Texas, US | 10 | 2005–2013 |
| Garland, Texas, US | 9 | 2014–2018 |
| Richardson, Texas, US | 2 | 2003–2006 |