Inventor
CHUNG-TING KO
Inventor
TW
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H01LSemiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
B82YSpecific uses or applications of nanostructures11%
C23CCoating metallic material4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
C03CChemical composition of glasses, glazes or vitreous enamels1%
H01JElectric discharge tubes or discharge lamps1%
PatentTitleYear
12,593,495Semiconductor device and method of manufacture202612,575,355Masking layer with post treatment202612,543,335Multilayer masking layer and method of forming same202612,527,047Isolation structure for transistors202612,501,690Hardmask formation with hybrid materials in semiconductor device202512,414,353Method for forming semiconductor structure202512,376,339Semiconductor device structure and method for forming the same202512,349,381Dielectric isolation structure for multi-gate transistors202512,328,929Method of forming thin dummy sidewall spacers for transistors with reduced pitches202512,324,185Semiconductor device, FinFET device and methods of forming the same202512,272,553Multi-layer photo etching mask including organic and inorganic materials202512,237,393Method of fabricating a semiconductor device202512,218,241Semiconductor device structure with etch stop layer for reducing RC delay202512,166,076Semiconductor device and methods of forming the same202412,166,035FinFET with bowl-shaped gate isolation and method202412,125,911Method of modulating stress of dielectric layers202412,113,113Semiconductor device with a core-shell feature and method for forming the same202412,112,942Deposition process for forming semiconductor device and system202412,112,988Hybrid isolation regions having upper and lower portions with seams202412,094,784Method for manufacturing semiconductor device202412,087,641Method for forming semiconductor structure with fins using a multilayer mask structure for etching to form nanostructures202412,087,834Semiconductor structure202412,080,553Semiconductor device and method of manufacture202412,062,578Prevention of contact bottom void in semiconductor fabrication202412,051,700Semiconductor device and method202412,027,423Forming isolation regions for separating fins and gate stacks202411,984,485Semiconductor device, FinFET device and methods of forming the same202411,948,843Method for forming hardmask formation by hybrid materials in semiconductor device202411,888,049Dielectric isolation structure for multi-gate transistors202411,855,185Multilayer masking layer and method of forming same202311,837,505Formation of hybrid isolation regions through recess and re-deposition202311,830,736Multi-layer photo etching mask including organic and inorganic materials202311,810,824Semiconductor device and manufacturing method thereof202311,725,278Systems and methods for a plasma enhanced deposition of material on a semiconductor substrate202311,728,173Masking layer with post treatment202311,600,530Semiconductor device and method of manufacture202311,532,628Semiconductor device and method202211,532,733Dielectric isolation structure for multi-gate transistors202211,532,507Semiconductor device and method202211,530,479Atomic layer deposition tool and method202211,532,475Deposition process for forming semiconductor device and system202211,502,196Stress modulation for dielectric layers202211,441,221Method of performing atomic layer deposition202211,437,277Forming isolation regions for separating fins and gate stacks202211,417,748Semiconductor device and method of fabricating a semiconductor device202211,404,323Formation of hybrid isolation regions through recess and re-deposition202211,362,003Prevention of contact bottom void in semiconductor fabrication202211,316,047Structure and formation method of semiconductor device with monoatomic etch stop layer202211,296,198Semiconductor structure with barrier layer and method for forming the same202211,271,083Semiconductor device, FinFET device and methods of forming the same202211,145,746Semiconductor device and method2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (51)· patent assignee history
2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO Y LTD (1)· patent assignee history
2021–2026Based in TW· patent location history
2025Patents assigned to TAIWAN SEMICODUCTOR MFG COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 51 | 2021–2026 |
| TAIWAN SEMICODUCTOR MFG COMPANY LTD | 1 | 2025 |
| TAIWAN SEMICONDUCTOR MFG CO Y LTD | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 51 | 2021–2026 |