Inventor
Ching-Wei Wu
Inventor
Chu-tung Town, TW
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores50%
H10BElectronic memory devices14%
H01LSemiconductor devices9%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
B23QDetails, components, or accessories for machine tools, e.g. arrangements for copying or controlling1%
G05BControl or regulating systems in general1%
H04JMultiplex communication1%
PatentTitleYear
10,770,135Memory macro which changes operational modes202010,755,770Circuit and method for writing to a bit cell202010,705,934Scan synchronous-write-through testing architectures for a memory device202010,706,934Failure detection circuitry for address decoder for a data storage device202010,553,300Method of detecting address decoding error and address decoder error detection system202010,354,731Failure detection circuitry for address decoder for a data storage device201910,186,313Memory macro disableable input-output circuits and methods of operating the same201910,141,059Failure detection circuitry for address decoder for a data storage device201810,090,032Word line driving unit with a boost voltage generator and memory device including the same201810,083,739Three-dimensional three-port bit cell and method of assembling same20189,851,915Two-stage read/write 3D architecture for memory devices20179,690,510'Two-stage read/write 3D architecture for memory devices'20179,666,302'System and method for memory scan design-for-test'20179,589,885'Device having multiple-layer pins in memory MUX1 layout'20179,490,005'Memory circuit and method for routing the memory circuit'20169,490,006'Time division multiplexed multiport memory'20169,455,025'Static random access memory and method of controlling the same'20169,281,311'Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same'20169,275,724'Method of writing to and reading data from a three-dimensional two port register file'20169,275,752'Read-only memory'20169,245,615'Boost system for dual-port SRAM'20169,230,622'Simultaneous two/dual port access on 6T SRAM'20169,183,907'Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell'20159,129,956'Device having multiple-layer pins in memory MUX1 layout'20159,064,604'Timing logic for memory array'20159,001,611'Three-dimensional two port register file'20158,845,247'Thermal compensation system for a milling machine'20148,837,192'N-bit rom cell'20148,675,435'Asymmetric sense amplifier design'20148,565,009'Access to multi-port devices'20138,488,395'Keepers, integrated circuits, and systems thereof'20138,437,210'Asymmetric sense amplifier design'20138,411,479'Memory circuits, systems, and methods for routing the memory circuits'20138,406,058'Read only memory and operating method thereof'20138,395,950'Memory device having a clock skew generator'20138,305,791'Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof'20127,952,911'SRAM cell array structure'20117,613,054'SRAM device with enhanced read/write operations'20097,502,277'Word-line driver design for pseudo two-port memories'20097,190,626'Memory system with bit-line discharging mechanism'20076,903,436'Multiple-time programmable electrical fuse utilizing MOS oxide breakdown'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (22)· patent assignee history
2005–2009Based in Hsinchu, TW· patent location history
2007–2011Based in Hsin Chu, TW· patent location history
2012–2014Patents assigned to WU CHING-WEI (8)· patent assignee history
2012–2013Patents assigned to LEE CHENG HUNG (4)· patent assignee history
2012–2020Based in Chu-tung Town, TW· patent location history
2013Patents assigned to CHEN KUANG TING (2)· patent assignee history
2014–2020Based in Nantou County, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (18)· patent assignee history
2017Based in Caotun Township, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 22 | 2005–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 18 | 2016–2020 |
| WU CHING-WEIself | 8 | 2012–2014 |
| LEE CHENG HUNG | 4 | 2012–2013 |
| CHEN KUANG TING | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chu-tung Town, TW | 24 | 2012–2020 |
| Nantou County, TW | 9 | 2014–2020 |
| Hsin Chu, TW | 3 | 2007–2011 |
| Caotun Township, TW | 2 | 2017 |
| Hsinchu, TW | 2 | 2005–2009 |