Inventor
Bruce W. McGaughy
Inventor
Fremont, CA, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing92%
G01RMeasuring electric variables3%
G06KGraphical data reading3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
10,339,240Adaptive high sigma yield prediction201910,002,217Region based device bypass in circuit simulation20189,804,894'Dynamic load balancing in circuit simulation'20179,779,192'Multi-rate parallel circuit simulation'20179,348,957'Repetitive circuit simulation'20169,031,825'Statistical circuit simulation'20158,819,086'Naming methodologies for a hierarchical system'20148,428,928'System and method for dynamically representing repetitive loads of a circuit during simulation'20138,326,591'Synchronized envelope and transient simulation of circuits'20128,260,600'Circuit simulator'20128,255,856'DC path checking in a hierarchical circuit design'20128,200,467'Adaptive solver for cyclic behavior of a circuit'20127,933,747'Method and system for simulating dynamic behavior of a transistor'20117,835,890'Hot carrier circuit reliability simulation'20107,836,419'Method and system for partitioning integrated circuits'20107,434,183'Method and system for validating a hierarchical simulation database'20087,415,403'Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure'20087,412,681'DC path checking in a hierarchical circuit design'20087,409,328'System and method for communicating simulation solutions between circuit components in a hierarchical data structure'20087,392,170'System and method for dynamically compressing circuit components during simulation'20087,373,289'Electrical isomorphism'20087,328,143'Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure'20087,299,428'Model stamping matrix check technique in circuit simulator'20077,292,968'Hot carrier circuit reliability simulation'20077,272,805'System and method for converting a flat netlist into a hierarchical netlist'20077,269,541'System and method for supporting multi-rate simulation of a circuit having hierarchical data structure'20077,266,479'System and method for high-order accurate device model approximation'20077,257,525'Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure'20077,243,313'System and method for reducing the size of RC circuits'20077,181,383'System and method for simulating a circuit having hierarchical structure'20077,143,021'Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure'20067,024,652'System and method for adaptive partitioning of circuit components during simulation'20066,928,626'System and method for modeling of circuit components'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2013Patents assigned to CADENCE DESIGN SYSTEMS INC (24)· patent assignee history
2005–2016Based in Fremont, CA, US· patent location history
2012–2019Patents assigned to PROPLUS DESIGN SOLUTIONS INC (7)· patent assignee history
2012–2016Patents assigned to MCGAUGHY BRUCE W (5)· patent assignee history
2012Patents assigned to CAI QIAN (2)· patent assignee history
2014–2018Patents assigned to PROPLUS ELECTRONICS CO LTD (4)· patent assignee history
2014–2019Based in Pleasanton, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 24 | 2005–2013 |
| PROPLUS DESIGN SOLUTIONS INC | 7 | 2012–2019 |
| MCGAUGHY BRUCE Wself | 5 | 2012–2016 |
| PROPLUS ELECTRONICS CO LTD | 4 | 2014–2018 |
| CAI QIAN | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 28 | 2005–2016 |
| Pleasanton, California, US | 5 | 2014–2019 |