Inventor
Binata Bhattacharyya
Inventor
Bangalore, IN
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing55%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use21%
H04LTransmission of digital information, e.g. telegraphic communication10%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications10%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy3%
PatentTitleYear
10,671,740Supporting configurable security levels for memory address ranges202010,230,528Tree-less integrity and replay memory protection for trusted execution environment201910,185,842Cache and data organization for memory protection201910,031,861Protect non-memory encryption engine (non-mee) metadata in trusted execution environment201810,007,606Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory20189,959,418Supporting configurable security levels for memory address ranges20189,893,881'Efficient sharing of hardware encryption pipeline for multiple security solutions'20189,720,488'Apparatus, method, and system for early deep sleep state exit of a processing element'20179,454,218'Apparatus, method, and system for early deep sleep state exit of a processing element'20169,032,125'Increasing turbo mode residency of a processor'20159,032,126'Increasing turbo mode residency of a processor'20158,990,602'Apparatus, method, and system for early deep sleep state exit of a processing element'20158,782,468'Methods and tools to debug complex multi-core, multi-socket QPI based system'20148,688,883'Increasing turbo mode residency of a processor'20147,836,229'Synchronizing control and data paths traversed by a data transaction'20107,761,696'Quiescing and de-quiescing point-to-point links'20107,600,080'Avoiding deadlocks in a multiprocessor system'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2020Patents assigned to INTEL CORP (17)· patent assignee history
2009–2019Based in Bangalore, IN· patent location history
2014–2015Patents assigned to BHATTACHARYYA BINATA (3)· patent assignee history
2014–2015Patents assigned to GUDDETI JAYAKRISHNA (3)· patent assignee history
2014Patents assigned to TIRUVALLUR KESHAVAN K (1)· patent assignee history
2015Based in Hillsboro, OR, US· patent location history
2018–2020Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 17 | 2009–2020 |
| BHATTACHARYYA BINATAself | 3 | 2014–2015 |
| GUDDETI JAYAKRISHNA | 3 | 2014–2015 |
| TIRUVALLUR KESHAVAN K | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 10 | 2009–2019 |
| Portland, OR, US | 5 | 2018–2020 |
| Hillsboro, OR, US | 2 | 2015 |