Inventor
Shankarram Athreya
Inventor
San Jose, CA, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1045%
C23CCoating metallic material27%
H03FAmplifiers9%
H10DInorganic electric semiconductor devices9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
PatentTitleYear
9,203,351'Offset cancellation with minimum noise impact and gain-bandwidth degradation'20157,569,501'ALD metal oxide deposition process using direct oxidation'20097,569,500'ALD metal oxide deposition process using direct oxidation'20097,067,439'ALD metal oxide deposition process using direct oxidation'20066,677,254'Processes for making a barrier between a dielectric and a conductor and products produced therefrom'20046,426,282'Method of forming solder bumps on a semiconductor wafer'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2009Patents assigned to APPLIED MATERIALS INC (5)· patent assignee history
2002–2004Based in Sunnyvale, CA, US· patent location history
2006–2015Based in San Jose, CA, US· patent location history
2015Patents assigned to MEGACHIPS CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 5 | 2002–2009 |
| MEGACHIPS CORP | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 4 | 2006–2015 |
| Sunnyvale, California, US | 2 | 2002–2004 |