LexDanaLexDanabeta
Inventor

Geng-Shin Shen

Inventor
Tainan, TW

Overview

55→
Patents
2008–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1062%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H01LSemiconductor devices7%
H05KPrinted circuits6%
Y02PClimate change mitigation technologies in the production or processing of goods3%
B82BNanostructures formed by manipulation of individual atoms, molecules, or limited collections of atoms or molecules as discrete units2%
B82YSpecific uses or applications of nanostructures2%
G06FElectric digital data processing2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
PatentTitleYear
9,307,676'Thermally enhanced electronic package'20169,159,685'Conductive structure and method for forming the same'20159,023,727'Method of manufacturing semiconductor packaging'20158,962,395'QFN package and manufacturing process thereof'20158,872,336'Conductive structure and method for forming the same'20148,809,088'Structure of stacking chips and method for manufacturing the same'20148,786,082'Semiconductor structure having no adjacent bumps between two adjacent pads'20148,736,060'Packaging structure'20148,712,932'Computer implemented apparatus for generating and filtering creative proposal'20148,564,954'Thermally enhanced electronic package'20138,431,478'Solder cap bump in semiconductor package and method of manufacturing the same'20138,431,437'Packaging method involving rearrangement of dice'20138,426,255'Chip package structure and method for manufacturing the same'20138,426,245'Packaging method involving rearrangement of dice'20138,245,193'Automatic creative proposal generating and filtering system and manufacturing method thereof and multiple components combining method'20128,212,347'Stacked chip package structure with leadframe having bus bar'20128,207,603'Stacked chip package structure with leadframe having inner leads with transfer pad'20128,169,061'Stacked chip package structure with leadframe having bus bar'20128,106,494'Leadframe for leadless package, structure and manufacturing method using the same'20128,105,876'Leadframe for leadless package, structure and manufacturing method using the same'20128,093,106'Method for manufacturing packaging structure'20128,058,109'Method for manufacturing a semiconductor structure'20117,981,725'Fabricating process of a chip package structure'20117,964,940'Chip package with asymmetric molding'20117,960,214'Chip package'20117,927,922'Dice rearrangement package structure using layout process to form a compliant configuration'20117,919,358'Method for fabricating multi-chip stacked package'20117,915,690'Die rearrangement package structure using layout process to form a compliant configuration'20117,902,649'Leadframe for leadless package, structure and manufacturing method using the same'20117,888,783'Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers'20117,851,896'Quad flat non-leaded chip package'20107,851,262'Manufacturing process for a chip package structure'20107,851,270'Manufacturing process for a chip package structure'20107,847,414'Chip package structure'20107,842,550'Method of fabricating quad flat non-leaded package'20107,834,432'Chip package having asymmetric molding'20107,816,771'Stacked chip package structure with leadframe having inner leads with transfer pad'20107,803,667'Manufacturing process for a quad flat non-leaded chip package structure'20107,803,666'Manufacturing process for a Quad Flat Non-leaded chip package structure'20107,795,079'Manufacturing process for a quad flat non-leaded chip package structure'20107,790,514'Manufacturing process for a chip package structure'20107,786,595'Stacked chip package structure with leadframe having bus bar'20107,749,806'Fabricating process of a chip package structure'20107,700,412'Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers'20107,696,629'Chip-stacked package structure'20107,662,667'Die rearrangement package structure using layout process to form a compliant configuration'20107,663,246'Stacked chip packaging with heat sink structure'20107,638,880'Chip package'20097,615,853'Chip-stacked package structure having leadframe with multi-piece bus bar'20097,576,416'Chip package having with asymmetric molding and turbulent plate downset design'20097,560,306'Manufacturing process for chip package without core'20097,538,419'Stacked-type chip package structure'20097,504,714'Chip package with asymmetric molding'20097,446,407'Chip package structure'20087,385,282'Stacked-type chip package structure'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2016Patents assigned to CHIPMOS TECHNOLOGIES INC (53)· patent assignee history
2008–2013Patents assigned to CHIPMOS TECHNOLOGIES BERMUDA (34)· patent assignee history
2008–2015Based in Tainan, TW· patent location history
2009–2016Based in Hsinchu, TW· patent location history
2011–2014Patents assigned to SHEN GENG-SHIN (12)· patent assignee history
2012–2015Patents assigned to SHEN GENG SHIN (4)· patent assignee history
2012Patents assigned to TU WU-CHANG (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CHIPMOS TECHNOLOGIES INC532008–2016
CHIPMOS TECHNOLOGIES BERMUDA342008–2013
SHEN GENG-SHINself122011–2014
SHEN GENG SHINself42012–2015
TU WU-CHANG32012
Locations
LocationPatentsSpan
Tainan, TW292008–2015
Hsinchu, TW262009–2016