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Inventor

James E. DeMaris

Inventor
Ridgefield, WA, US

Overview

6→
Patents
1992–2017
Patent span
Physics
Primary field (CPC G)

Patents· 6 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores43%
H03KPulse technique29%
G06FElectric digital data processing14%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%
PatentTitleYear
9,772,668'Power shutdown with isolation logic in I/O power domain'20177,606,092'Testing for SRAM memory data retention'20096,744,659'Source-biased memory cell array'20046,618,309'Adjustable memory self-timing circuit'20035,136,189'BiCMOS input circuit for detecting signals out of ECL range'19925,103,121'Input buffer regenerative latch for ECL levels'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992Patents assigned to NAT SEMICONDUCTOR CORP (2)· patent assignee history
1992Based in Brush Prairie, WA, US· patent location history
2003–2009Patents assigned to ANALOG DEVICES INC (3)· patent assignee history
2003–2009Based in Ridgefield, WA, US· patent location history
2017Patents assigned to CADENCE DESIGN SYSTEMS INC (1)· patent assignee history
2017Based in Fuquay-Varina, NC, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ANALOG DEVICES INC32003–2009
NAT SEMICONDUCTOR CORP21992
CADENCE DESIGN SYSTEMS INC12017
Locations
LocationPatentsSpan
Ridgefield, Washington, US32003–2009
Brush Prairie, Washington, US21992
Fuquay-Varina, NC, US12017