Inventor
James H. Scheuneman
Inventor
St. Paul, MN, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing86%
G11CStatic stores11%
G01RMeasuring electric variables4%
PatentTitleYear
5,068,782'Accessing control with predetermined priority based on a feedback arrangement'19915,060,145'Memory access system for pipelined data paths to and from storage'19914,996,688'Fault capture/fault injection system'19914,989,210'Pipelined address check bit stack controller'19914,962,501'Bus data transmission verification system'19904,953,131'Unconditional clock and automatic refresh logic'19904,926,426'Error correction check during write cycles'19904,918,695'Failure detection for partial write operations for memories'19904,918,696'Bank initiate error detection'19904,757,440'Pipelined data stack with access through-checking'19884,727,510'System for addressing a multibank memory system'19884,722,052'Multiple unit adapter'19884,697,233'Partial duplication of pipelined stack with data integrity checking'19874,652,993'Multiple output port memory storage module'19874,649,475'Multiple port memory with port decode error detector'19874,633,434'High performance storage unit'19864,600,986'Pipelined split stack with high performance interleaved decode'19864,531,213'Memory through checking system with comparison of data word parity before and after ECC processing'19854,357,686'Hidden memory refresh'19824,292,674'One word buffer memory system'19814,163,147'Double bit error correction using double bit complementing'19794,139,148'Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory'19794,112,502'Conditional bypass of error correction for dual memory access time selection'19784,092,713'Post-write address word correction in cache memory system'19784,070,706'Parallel requestor priority determination and requestor address matching in a cache memory system'19784,058,851'Conditional bypass of error correction for dual memory access time selection'1977Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1977–1979Patents assigned to SPERRY RAND CORP (6)· patent assignee history
1977–1991Based in St. Paul, MN, US· patent location history
1981–1988Patents assigned to SPERRY CORP (8)· patent assignee history
1987–1991Patents assigned to UNISYS CORP (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNISYS CORP | 12 | 1987–1991 |
| SPERRY CORP | 8 | 1981–1988 |
| SPERRY RAND CORP | 6 | 1977–1979 |
Locations
| Location | Patents | Span |
|---|---|---|
| St. Paul, Minnesota, US | 26 | 1977–1991 |