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Inventor

Ruban Kanapathippillai

Inventor
Dublin, CA, US

Overview

25→
Patents
2003–2018
Patent span
Physics
Primary field (CPC G)

Patents· 25 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores27%
G06FElectric digital data processing22%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
H04LTransmission of digital information, e.g. telegraphic communication9%
H01RElectrically-conductive connections8%
H05KPrinted circuits8%
Y02PClimate change mitigation technologies in the production or processing of goods8%
Y10TTechnical subjects covered by former us classification8%
PatentTitleYear
9,905,303'Front/back control of integrated circuits for flash dual inline memory modules'20189,336,835'Flash dual inline memory modules with multiplexing support circuits'20169,318,156'Multi-chip packaged flash memory/support application specific integrated circuit for flash dual inline memory modules'20168,881,389'Methods of flash dual inline memory modules with flash memory'20148,719,465'Method and apparatus for distributed direct memory access for systems on chip'20148,706,932'Replaceable non-volatile memory apparatus with a plurality of pluggable electrical connectors'20148,689,042'Methods for data redundancy across replaceable non-volatile memory storage devices'20148,650,343'Methods for upgrading, diagnosing, and maintaining replaceable non-volatile memory'20148,639,863'Memory apparatus for replaceable non-volatile memory'20148,386,665'Method and apparatus for distributed direct memory access for systems on chip'20138,189,328'Methods and apparatus of dual inline memory modules for flash memory'20127,970,961'Method and apparatus for distributed direct memory access for systems on chip'20117,502,977'Method and apparatus for reconfigurable memory'20097,490,260'Method and apparatus for reconfigurable memory'20097,464,197'Distributed direct memory access for systems on chip'20087,318,115'IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic'20087,287,148'Unified shared pipeline allowing deactivation of RISC/DSP units for power saving'20077,233,166'Bus state keepers'20077,155,541'Tables with direct memory access descriptor lists for distributed direct memory access'20067,111,190'Method and apparatus for reconfigurable memory'20066,944,087'Method and apparatus for off boundary memory access'20056,874,039'Method and apparatus for distributed direct memory access for systems on chip'20056,785,184'Self-timed activation logic for memory'20046,732,203'Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus'20046,618,313'Self-timed activation logic for memory'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2014Patents assigned to INTEL CORP (16)· patent assignee history
2003–2013Based in Dublin, CA, US· patent location history
2012–2016Patents assigned to KANAPATHIPPILLAI RUBAN (9)· patent assignee history
2012–2018Patents assigned to VIRIDENT SYSTEMS INC (9)· patent assignee history
2012–2018Based in Pleasanton, CA, US· patent location history
2014Patents assigned to KARAMCHETI VIJAY (4)· patent assignee history
2014Patents assigned to NARASIMHA ASHWIN (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP162003–2014
KANAPATHIPPILLAI RUBANself92012–2016
VIRIDENT SYSTEMS INC92012–2018
KARAMCHETI VIJAY42014
NARASIMHA ASHWIN42014
Locations
LocationPatentsSpan
Dublin, California, US152003–2013
Pleasanton, California, US102012–2018