Inventor
Wei-Chung Lo
Inventor
Taipei, TW
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
H01LSemiconductor devices17%
H10HInorganic light-emitting semiconductor devices having potential barriers11%
H05KPrinted circuits6%
Y10TTechnical subjects covered by former us classification6%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form3%
F21SNon-portable lighting devices3%
F21VFunctional features or details of lighting devices or systems thereof3%
F21YIndexing scheme associated with subclasses f21k, f21l, f21s and f21v, relating to the form or the kind of the light sources or of the colour of the light emitted3%
G02BOptical elements, systems or apparatus3%
PatentTitleYear
10,867,907Package substrate and method of fabricating the same202010,276,908Electromagnetic wave transmission board and differential electromagnetic wave transmission board201910,068,847Package substrate and method of fabricating the same20189,931,813Bonding structure and method of fabricating the same20189,647,029'Light-emitting device and manufacturing method of a display'20179,485,874'Package substrate having photo-sensitive dielectric layer and method of fabricating the same'20169,252,054'Thinned integrated circuit device and manufacturing process for the same'20169,111,774'Wafer-to-wafer stack with supporting post'20158,915,634'Plane light source and flexible plane light source'20148,810,031'Wafer-to-wafer stack with supporting pedestal'20148,679,891'Heterostructure containing IC and LED and method for fabricating the same'20148,536,613'Heterostructure containing IC and LED and method for fabricating the same'20138,304,666'Structure of multiple coaxial leads within single via in substrate and manufacturing method thereof'20128,164,165'Wafer-to-wafer stack with supporting pedestal'20128,049,330'Wafer-level chip scale packaging for LED comprising carrier substrate with thermally conductive through holes and fill channels'20118,039,935'Wafer level chip scale packaging structure and method of fabricating the same'20117,948,072'Wafer-to-wafer stacking'20117,329,563'Method for fabrication of wafer level package incorporating dual compliant layers'20086,914,333'Wafer level package incorporating dual compliant layers and method for fabrication'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2020Patents assigned to IND TECH RES INST (17)· patent assignee history
2005–2008Based in Junghe, TW· patent location history
2011–2020Based in Taipei, TW· patent location history
2011–2018Based in Hsinchu, TW· patent location history
2011Based in Zhonghe, TW· patent location history
2012–2014Patents assigned to LO WEI-CHUNG (5)· patent assignee history
2012–2014Patents assigned to CHANG CHI-SHIH (2)· patent assignee history
2012–2014Patents assigned to CHEN YU-HUA (2)· patent assignee history
2016–2020Patents assigned to UNIMICRON TECHNOLOGY CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IND TECH RES INST | 17 | 2005–2020 |
| LO WEI-CHUNGself | 5 | 2012–2014 |
| UNIMICRON TECHNOLOGY CORP | 3 | 2016–2020 |
| CHANG CHI-SHIH | 2 | 2012–2014 |
| CHEN YU-HUA | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 10 | 2011–2020 |
| Hsinchu, TW | 6 | 2011–2018 |
| Junghe, TW | 2 | 2005–2008 |
| Zhonghe, TW | 1 | 2011 |