Inventor
Patrick E. Perry
Inventor
Shelburne, VT, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing41%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%
H03KPulse technique10%
G11BInformation storage based on relative movement between record carrier and transducer7%
G11CStatic stores7%
G01RMeasuring electric variables3%
G05FSystems for regulating electric or magnetic variables3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods3%
PatentTitleYear
9,734,920'Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories'20179,224,503'Memory test with in-line error correction code logic'20156,880,074'In-line code suppression'20056,802,033'Low-power critical error rate communications controller'20046,711,719'Method and apparatus for reducing power consumption in VLSI circuit designs'20046,678,847'Real time function view system and method'20046,479,974'Stacked voltage rails for low-voltage DC distribution'20026,477,654'Managing VT for reduced power using power setting commands in the instruction stream'20026,317,840'Control of multiple equivalent functional units for power reduction'20016,269,468'Split I/O circuit for performance optimization of digital circuits'20016,097,243'Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode'20006,026,224'Redundant vias'20006,011,383'Low powering apparatus for automatic reduction of power in active and standby modes'20005,874,833'True/complement output bus for reduced simulataneous switching noise'19995,784,575'Output driver that parks output before going tristate'19985,341,310'Wiring layout design method and system for integrated circuits'19945,182,468'Current limiting clamp circuit'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2017Patents assigned to IBM (17)· patent assignee history
1993–1994Based in Colchester, VT, US· patent location history
1998–2004Based in Essex Junction, VT, US· patent location history
2000–2017Based in Shelburne, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 1993–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Shelburne, VT, US | 10 | 2000–2017 |
| Essex Junction, VT, US | 5 | 1998–2004 |
| Colchester, VT, US | 2 | 1993–1994 |