Inventor
YOAV WEINBERG
Inventor
CA
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing48%
G11CStatic stores26%
H03MCoding14%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H03KPulse technique1%
PatentTitleYear
12,572,309Command timer interrupt202612,561,201Error protection for managed memory devices202612,511,059Power efficient codeword scrambling in a non-volatile memory device202512,499,010Cryptographic data integrity protection202512,450,166Caching host memory address translation data in a memory sub-system202512,437,788Syndrome decoding system202512,405,726Managing write command execution during a power failure in a memory sub-system202512,301,254Early stopping of bit-flip low density parity check decoding based on syndrome weight202512,292,795Data recovery using ordered data requests202512,243,600Voltage detection for managed memory systems202512,182,046Data burst suspend mode using pause detection202412,169,461Status check using chip enable pin202412,170,124Scan-based voltage frequency scaling202412,159,667Internal reference resistor for non-volatile memory202412,111,781Data burst suspend mode using multi-level signaling202412,088,301Resetting integrated circuits202412,073,121Command timer interrupt202412,072,764Command and data path error protection202412,067,264Power efficient codeword scrambling in a non-volatile memory device202412,014,071Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism202412,001,279Error protection for managed memory devices202411,996,860Scaled bit flip thresholds across columns for irregular low density parity check decoding202411,962,500Data packet management202411,915,771Voltage detection for managed memory systems202411,914,473Data recovery using ordered data requests202411,860,714Error notification using an external channel202411,750,218Iterative error correction with adjustable parameters after a threshold number of iterations202311,693,732Cryptographic data integrity protection202311,675,709Reading sequential data from memory using a pivot table202311,669,456Cache release command for cache reads in a memory sub-system202311,650,931Hybrid logical to physical caching scheme of L2P cache and L2P changelog202311,636,904Almost ready memory management202311,632,132Configuring iterative error correction parameters using criteria from previous iterations202311,500,791Status check using chip enable pin202211,431,629Data packet management202211,394,403Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices202211,374,592Iterative error correction with adjustable parameters after a threshold number of iterations202211,188,473Cache release command for cache reads in a memory sub-system202111,151,052Reading sequential data from memory using a pivot table202111,146,291Configuring iterative error correction parameters using criteria from previous iterations2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (40)· patent assignee history
2021–2026Based in CA· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 40 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| CA | 40 | 2021–2026 |