Inventor

Jason W. Klaus

Inventor
Portland, OR, US

Overview

27→
Patents
2000–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 27 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
G06FElectric digital data processing12%
H01LSemiconductor devices11%
G11CStatic stores9%
C23CCoating metallic material8%
B01DSeparation3%
PatentTitleYear
10,629,483Self-aligned contacts202010,141,226Self-aligned contacts20189,892,967'Self-aligned contacts'20189,508,821'Self-aligned contacts'20169,466,565'Self-aligned contacts'20169,244,842'Data storage device with copy command'20169,093,513'Self-aligned contacts'20159,054,178'Self-aligned contacts'20158,595,572'Data storage device with metadata command'20138,578,084'Data storage device having multiple removable memory boards'20138,436,404'Self-aligned contacts'20138,433,845'Data storage device which serializes memory device ready/busy signals'20138,327,220'Data storage device with verify on write command'20128,294,223'Metal gate structure and method of manufacturing same'20128,239,724'Error correction for a data storage device'20128,239,713'Data storage device with bad block scan command'20128,239,729'Data storage device with copy command'20128,178,436'Adhesion and electromigration performance at an interface between a dielectric and metal'20128,088,665'Method of forming self-aligned low resistance contact layer'20127,875,519'Metal gate structure and method of manufacturing same'20117,816,218'Selective deposition of amorphous silicon films on metal gates'20107,759,262'Selective formation of dielectric etch stop layers'20106,958,174'Solid material comprising a thin metal film on its surface and methods for producing the same'20056,818,250'Method for forming SIO2 by chemical vapor deposition at room temperature'20046,090,442'Method of growing films on substrates at room temperatures using catalyzed binary reaction sequence chemistry'20006,051,517'Modified zeolite membrane'20006,043,177'Modification of zeolite or molecular sieve membranes using atomic layer controlled chemical vapor deposition'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000Based in Boulder, CO, US· patent location history
2004–2020Based in Portland, OR, US· patent location history
2010–2020Patents assigned to INTEL CORP (14)· patent assignee history
2012–2015Patents assigned to KLAUS JASON W (11)· patent assignee history
2012–2016Patents assigned to GOOGLE INC (8)· patent assignee history
2012–2013Patents assigned to BORCHERS ALBERT T (7)· patent assignee history
2012–2013Patents assigned to SPRINKLE ROBERT S (7)· patent assignee history
2012–2016Based in Brooklyn, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP142010–2020
KLAUS JASON Wself112012–2015
GOOGLE INC82012–2016
BORCHERS ALBERT T72012–2013
SPRINKLE ROBERT S72012–2013
Locations
LocationPatentsSpan
Portland, OR, US162004–2020
Brooklyn, New York, US82012–2016
Boulder, CO, US32000