Inventor

Bijan Davari

Inventor

Mahopac, NY, US

Overview

1986–2018

Patent span

Electricity

Primary field (CPC H)

Patents· 19 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices21%

H10BElectronic memory devices14%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%

G11CStatic stores5%

H04LTransmission of digital information, e.g. telegraphic communication5%

H04WWireless communication networks5%

C25DProcesses for the electrolytic or electrophoretic production of coatings2%

G01RMeasuring electric variables2%

PatentTitleYear

10,085,157Reconfiguring a mobile network based on cellular network state information2018 9,838,108IP based real-time communications over a mobile network2017 7,974,826'Energy system modeling apparatus and methods'2011 7,356,383'Methods and apparatus for optimizing combined cycle/combined process facilities'2008 6,800,518'Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering'2004 6,756,257'Patterned SOI regions on semiconductor chips'2004 6,566,177'Silicon-on-insulator vertical array device trench capacitor DRAM'2003 6,426,252'Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap'2002 6,337,253'Process of making buried capacitor for silicon-on-insulator structure'2002 6,333,532'Patterned SOI regions in semiconductor chips'2001 6,188,122'Buried capacitor for silicon-on-insulator structure'2001 6,087,199'Method for fabricating a very dense chip package'2000 5,998,868'Very dense chip package'1999 5,784,311'Two-device memory cell on SOI for merged logic and memory applications'1998 5,541,427'SRAM cell with capacitor'1996 4,889,819'Method for fabricating shallow junctions by preamorphizing with dopant of same conductivity as substrate'1989 4,881,105'Integrated trench-transistor structure and fabrication process'1989 4,621,233'Non-destructive testing of semiconductors using acoustic wave method'1986 4,569,728'Selective anodic oxidation of semiconductors for pattern generation'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986Patents assigned to RENSSELAER POLYTECH INST (1)· patent assignee history

1986Patents assigned to US AIR FORCE (1)· patent assignee history

1986Based in Troy, NY, US· patent location history

1986Based in Peekskill, NY, US· patent location history

1989–2018Patents assigned to IBM (15)· patent assignee history

1989–2018Based in Mahopac, NY, US· patent location history

2008–2011Patents assigned to GEN ELECTRIC (2)· patent assignee history

2008–2011Based in Fremont, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	15	1989–2018
GEN ELECTRIC	2	2008–2011
RENSSELAER POLYTECH INST	1	1986
US AIR FORCE	1	1986

Locations

Location	Patents	Span
Mahopac, New York, US	15	1989–2018
Fremont, California, US	2	2008–2011
Troy, New York, US	1	1986
Peekskill, New York, US	1	1986