Inventor

HIDEHIRO FUJIWARA

Inventor

TW

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 85 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores26%

H10BElectronic memory devices15%

H01LSemiconductor devices14%

H10DInorganic electric semiconductor devices12%

G06FElectric digital data processing11%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

H03KPulse technique3%

G06NComputing arrangements based on specific computational models3%

G01RMeasuring electric variables2%

G05FSystems for regulating electric or magnetic variables2%

PatentTitleYear

12,596,494Integrated circuit and method of forming the same2026 12,587,175Reduced power consumption compute-in-memory system, method of operating same2026 12,586,635Static random access memory with write assist circuit2026 12,586,628Adjusting pulse width based on address signal in memory devices2026 12,581,635Integrated circuit device and method2026 12,541,319Computing-in-memory device and method2026 12,542,177Memory device and method for computing-in- memory (CIM)2026 12,531,549Latch circuits and methods for operating the same2026 12,525,261Memory devices with reduced bit line capacitance and methods of manufacturing thereof2026 12,520,4704CPP SRAM cell and array2026 12,511,102Memory device and method for computing-in-memory (CIM)2025 12,494,235Systems and methods for flexible bank addressing in digital computing-in-memory (DCIM)2025 12,475,934Memory device and method for operating memory device2025 12,431,192Semiconductor device2025 12,412,621Semiconductor device including distributed write driving arrangement2025 12,408,316Memory array circuit and method of manufacturing same2025 12,387,768Memory device including separate negative bit line2025 12,380,946Memory computation method2025 12,373,131Data sequencing circuit and method2025 12,369,292Memory device2025 12,367,929Memory device having a negative voltage circuit2025 12,346,143Voltage regulator with power rail tracking2025 12,334,145Bitcell supporting bit-write-mask function2025 12,308,303Integrated circuit die with memory macro including through-silicon via and method of forming the same2025 12,260,903Memory devices with improved bit line loading2025 12,260,897Separated read BL scheme in 3T dram for read speed improvement2025 12,260,904Memory device with additional write bit lines2025 12,261,152Vertical interconnect structures in three-dimensional integrated circuits2025 12,245,412SRAM cell word line structure with reduced RC effects2025 12,230,318Memory device including a word line with portions with different sizes in different metal layers2025 12,164,882In-memory computation circuit and method2024 12,159,688Systems and methods for memory operation using local word lines2024 12,147,784Compute in memory2024 12,137,548Four CPP wide memory cell with buried power grid, and method of fabricating same2024 12,136,466Header layout design including backside power rail2024 12,125,523Memory device and method of manufacturing the same2024 12,100,436Method and system to balance ground bounce2024 12,080,341Memory device including dual control circuits2024 12,074,156Memory array circuit and method of manufacturing same2024 12,029,023Memory array circuit and method of manufacturing same2024 11,997,8434CPP SRAM cell and array2024 11,989,046Voltage regulator with power rail tracking2024 11,978,723Vertical interconnect structures in three-dimensional integrated circuits2024 11,961,554Shared power footer circuit2024 11,948,627Static random access memory with write assist circuit2024 11,935,586Memory device and method for computing-in-memory (CIM)2024 11,929,116Memory device having a negative voltage circuit2024 11,908,545Memory device and operating method for computing-in-memory2024 11,910,587Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure2024 11,853,596Data sequencing circuit and method2023 11,854,943Memory macro including through-silicon via2023 11,830,543Memory computation circuit2023 11,805,636Memory device2023 11,783,890Semiconductor device including distributed write driving arrangement2023 11,778,802SRAM cell word line structure with reduced RC effects2023 11,769,533Semiconductor chip having memory and logic cells2023 11,714,570Computing-in-memory device and method2023 11,715,501Header layout design including backside power rail2023 11,682,440Systems and methods for memory operation using local word lines2023 11,657,870Method and system to balance ground bounce2023 11,651,134Method of certifying safety levels of semiconductor memories in integrated circuits2023 11,637,108Memory array circuit and method of manufacturing same2023 11,631,456Bitcell supporting bit-write-mask function2023 11,579,648Voltage regulator with power rail tracking2023 11,569,246Four CPP wide memory cell with buried power grid, and method of fabricating same2023 11,562,786Memory device having a negative voltage circuit2023 11,562,946Memory macro including through-silicon via2023 11,532,351Memory device with additional write bit lines2022 11,482,276System and method for read speed improvement in 3T DRAM2022 11,423,977Static random access memory with write assist circuit2022 11,423,974Method of forming semiconductor device including distributed write driving arrangement2022 11,404,115Memory with write assist scheme2022 11,404,113Memory device including a word line with portions with different sizes in different metal layers2022 11,398,257Header layout design including backside power rail2022 11,398,275Memory computation circuit and method2022 11,322,198Multi word line assertion2022 11,308,999Boost bypass circuitry in a memory storage device2022 11,263,331Electronic device for checking randomness of identification key device, random key checker circuit, and method of checking randomness of electronic device2022 11,264,070Systems and methods for memory operation using local word lines2022 11,199,866Voltage regulator with power rail tracking2021 11,183,234Bitcell supporting bit-write-mask function2021 11,176,997Memory cell2021 11,152,057SRAM memory2021 11,152,301Memory cell having multi-level word line2021 11,139,040Method of detecting address decoding error2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (84)· patent assignee history

2021–2026Based in TW· patent location history

2023–2025Patents assigned to TSMC NANJING COMPANY LTD (3)· patent assignee history

2023Patents assigned to TSMC CHINA COMPANY LTD (1)· patent assignee history

2026Patents assigned to TAIWAN SEMICONDUCTOR MFG COMPANY LTD (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	84	2021–2026
TSMC NANJING COMPANY LTD	3	2023–2025
TAIWAN SEMICONDUCTOR MFG COMPANY LTD	1	2026
TSMC CHINA COMPANY LTD	1	2023

Locations

Location	Patents	Span
TW	85	2021–2026