Inventor
Ming-Jie Huang
Inventor
Hsinchu, TW
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices39%
H01LSemiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10BElectronic memory devices7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
PatentTitleYear
10,868,166Highly strained source/drain trenches in semiconductor devices202010,867,807Semiconductor device and method202010,186,511Metal gate isolation structure and method forming same201910,134,604Semiconductor device and method20189,917,085'Metal gate isolation structure and method forming same'20189,543,210'Forming crown active regions for FinFETs'20179,412,666'Equal gate height control method for semiconductor device with different pattern densites'20169,214,358'Equal gate height control method for semiconductor device with different pattern densites'20159,130,058'Forming crown active regions for FinFETs'20158,900,957'Method of dual epi process for semiconductor device'20148,900,956'Method of dual EPI process for semiconductor device'20148,877,614'Spacer for semiconductor structure contact'20148,835,242'Semiconductor structure and method'20148,692,353'Semiconductor structure and method'20148,609,497'Method of dual EPI process for semiconductor device'20138,563,439'Method of pitch dimension shrinkage'20138,501,570'Method of manufacturing source/drain structures'20138,329,546'Modified profile gate structure for semiconductor device and methods of forming thereof'20128,071,481'Method for forming highly strained source/drain trenches'20118,048,764'Dual etch method of defining active area in semiconductor device'20117,141,460'Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers'20067,115,450'Approach to improve line end shortening including simultaneous trimming of photosensitive layer and hardmask'20067,060,628'Method for fabricating a hard mask polysilicon gate'20067,008,866'Large-scale trimming for ultra-narrow gates'20066,828,205'Method using wet etching to trim a critical dimension'20046,794,230'Approach to improve line end shortening'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (19)· patent assignee history
2004–2020Based in Hsinchu, TW· patent location history
2011–2015Patents assigned to HUANG MING-JIE (8)· patent assignee history
2013–2015Patents assigned to CHEN CHEN-PING (2)· patent assignee history
2014Patents assigned to CHEN JYH-HUEI (2)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 19 | 2004–2015 |
| HUANG MING-JIEself | 8 | 2011–2015 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 7 | 2016–2020 |
| CHEN CHEN-PING | 2 | 2013–2015 |
| CHEN JYH-HUEI | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 26 | 2004–2020 |