LexDanaLexDanabeta
Inventor

Shay Gueron

Inventor
Haifa, IL

Overview

121→
Patents
2010–2021
Patent span
Physics
Primary field (CPC G)

Patents· 121 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing47%
H04LTransmission of digital information, e.g. telegraphic communication37%
G11CStatic stores10%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy3%
H03MCoding2%
G01RMeasuring electric variables0%
H04WWireless communication networks0%
PatentTitleYear
11,128,443SM3 hash algorithm acceleration processors, methods, systems, and instructions202111,108,552Data encryption method and system202111,085,964Systems and methods for intellectual property-secured, remote debugging202111,075,746SM3 hash algorithm acceleration processors, methods, systems, and instructions202110,963,593Secure data storage using multiple factors202110,922,243Secure memory202110,776,525Multi-tenant cryptographic memory isolation202010,623,175SM3 hash algorithm acceleration processors, methods, systems, and instructions202010,615,963Architecture and instruction set for implementing advanced encryption standard (AES)202010,601,583Architecture and instruction set for implementing advanced encryption standard (AES)202010,594,475Architecture and instruction set for implementing advanced encryption standard (AES)202010,594,474Architecture and instruction set for implementing advanced encryption standard (AES)202010,587,395Architecture and instruction set for implementing advanced encryption standard (AES)202010,581,590Flexible architecture and instruction for advanced encryption standard (AES)202010,567,160Architecture and instruction set for implementing advanced encryption standard (AES)202010,567,161Architecture and instruction set for implementing advanced encryption standard AES202010,560,259Architecture and instruction set for implementing advanced encryption standard (AES)202010,560,258Architecture and instruction set for implementing advanced encryption standard (AES)202010,554,386Flexible architecture and instruction for advanced encryption standard (AES)202010,554,387Architecture and instruction set for implementing advanced encryption standard (AES)202010,514,912Vector multiplication with accumulation in large register space201910,476,667SM4 acceleration processors, methods, systems, and instructions201910,469,249SM4 acceleration processors, methods, systems, and instructions201910,454,669SM4 acceleration processors, methods, systems, and instructions201910,447,468SM4 acceleration processors, methods, systems, and instructions201910,432,393Architecture and instruction set for implementing advanced encryption standard (AES)201910,425,222SM4 acceleration processors, methods, systems, and instructions201910,419,210SM4 acceleration processors, methods, systems, and instructions201910,372,625Secure memory201910,313,107Flexible architecture and instruction for advanced encryption standard (AES)201910,291,394Flexible architecture and instruction for advanced encryption standard (AES)201910,270,589Flexible architecture and instruction for advanced encryption standard (AES)201910,263,769Flexible architecture and instruction for advanced encryption standard (AES)201910,256,972Flexible architecture and instruction for advanced encryption standard (AES)201910,256,971Flexible architecture and instruction for advanced encryption standard (AES)201910,248,579Method, apparatus, and instructions for safely storing secrets in system memory201910,248,486Memory monitor201910,187,201Flexible architecture and instruction for advanced encryption standard (AES)201910,181,945Flexible architecture and instruction for advanced encryption standard (AES)201910,171,231Flexible architecture and instruction for advanced encryption standard (AES)201910,171,232Flexible architecture and instruction for advanced encryption standard (AES)201910,164,769Flexible architecture and instruction for advanced encryption standard (AES)201810,158,478Flexible architecture and instruction for advanced encryption standard (AES)201810,148,426Method and apparatus for efficiently implementing the advanced encryption standard201810,095,516Vector multiplication with accumulation in large register space201810,050,778Method and apparatus for efficiently implementing the advanced encryption standard201810,015,010SM4 acceleration processors, methods, systems, and instructions20189,990,314Instructions and logic to interrupt and resume paging in a secure enclave page cache20189,979,538SM3 hash algorithm acceleration processors, methods, systems, and instructions20189,965,276Vector operations with operand base system conversion and re-conversion20189,960,907Instruction for Performing SIMD affine transformation20189,906,359'Instructions and logic to provide general purpose GF(256) SIMD cryptographic arithmetic functionality'20189,800,406'Technologies for modifying a first cryptographic cipher with operations of a second cryptographic cipher'20179,766,888'Processor instruction to store indexes of source data elements in positions representing a sorted order of the source data elements'20179,703,733'Instructions and logic to interrupt and resume paging in a secure enclave page cache'20179,654,282'Flexible architecture and instruction for advanced encryption standard (AES)'20179,654,281'Flexible architecture and instruction for advanced encryption standard (AES)'20179,647,831'Flexible architecture and instruction for advanced encryption standard (AES)'20179,641,320'Flexible architecture and instruction for advanced encryption standard (AES)'20179,641,319'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,829'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,828'Flexible architecture and instruction for advanced encryption standard (AES)'20179,634,830'Flexible architecture and instruction for advanced encryption standard (AES)'20179,559,848'Method, apparatus, and instructions for safely storing secrets in system memory'20179,544,133'On-the-fly key generation for encryption and decryption'20179,524,240'Obscuring memory access patterns in conjunction with deadlock detection or avoidance'20169,513,913'SM4 acceleration processors, methods, systems, and instructions'20169,383,966'Number squaring computer-implemented method and apparatus'20169,355,068'Vector multiplication with operand base system conversion and re-conversion'20169,325,498'Performing AES encryption or decryption in multiple modes with a single instruction'20169,317,719'SM3 hash algorithm acceleration processors, methods, systems, and instructions'20169,276,750'Secure processing environment measurement and attestation'20169,268,564'Vector and scalar based modular exponentiation'20169,230,120'Architecture and instruction set for implementing advanced encryption standard (AES)'20169,158,902'Software modification for partial secure memory processing'20159,076,019'Method and apparatus for memory encryption with integrity check and protection against replay attacks'20159,047,082'Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations'20159,043,604'Method and apparatus for key provisioning of hardware devices'20158,923,510'Method and apparatus for efficiently implementing the advanced encryption standard'20148,913,740'Method and apparatus for generating an Advanced Encryption Standard (AES) key schedule'20148,879,725'Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation'20148,869,294'Mitigating branch prediction and other timing based side channel attacks'20148,855,299'Executing an encryption instruction using stored round keys'20148,856,547'Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures'20148,856,546'Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures'20148,832,457'Methods and apparatus for authenticating components of processing systems'20148,804,951'Speeding up galois counter mode (GCM) computations'20148,799,343'Modular exponentiation with partitioned and scattered storage of Montgomery Multiplication results'20148,787,565'Method and apparatus for generating an advanced encryption standard (AES) key schedule'20148,776,248'Method and apparatus for booting a processing system'20148,732,548'Instruction-set architecture for programmable cyclic redundancy check (CRC) computations'20148,689,078'Determining a message residue'20148,634,550'Architecture and instruction set for implementing advanced encryption standard (AES)'20148,600,049'Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation'20138,538,015'Flexible architecture and instruction for advanced encryption standard (AES)'20138,538,012'Performing AES encryption or decryption in multiple modes with a single instruction'20138,516,201'Protecting private data from cache attacks'20138,489,660'Digital random number generator using partially entropic data'20138,468,365'Tweakable encryption mode for memory encryption with protection against replay attacks'20138,464,125'Instruction-set architecture for programmable cyclic redundancy check (CRC) computations'20138,442,217'Method of implementing one way hash functions and apparatus therefor'20138,407,425'Obscuring memory access patterns in conjunction with deadlock detection or avoidance'20138,364,975'Methods and apparatus for protecting data'20138,341,356'Protected cache architecture and secure programming paradigm to protect applications'20128,340,280'Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations'20128,219,797'Method and system to facilitate configuration of a hardware device in a platform'20128,214,414'Combined set bit count and detector logic'20128,209,689'Live lock free priority scheme for memory transactions in transactional memory'20128,209,542'Methods and apparatus for authenticating components of processing systems'20128,194,854'Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation'20128,150,031'Method and apparatus to perform redundant array of independent disks (RAID) operations'20128,144,864'Method for speeding up the computations for characteristic 2 elliptic curve cryptographic systems'20128,127,363'Method and apparatus for booting a processing system'20128,068,614'Methods and apparatus for batch bound authentication'20118,042,025'Determining a message residue'20118,010,587'Random number generator'20117,991,152'Speeding up Galois Counter Mode (GCM) computations'20117,958,320'Protected cache architecture and secure programming paradigm to protect applications'20117,949,130'Architecture and instruction set for implementing advanced encryption standard (AES)'20117,760,873'Method and a system for a quick verification rabin signature scheme'20107,760,875'Accelerating Diffie-Hellman key-exchange protocol with zero-biased exponent windowing'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2021Patents assigned to INTEL CORP (119)· patent assignee history
2010–2021Based in Haifa, IL· patent location history
2011–2018Patents assigned to GUERON SHAY (43)· patent assignee history
2012–2016Patents assigned to ANATI ITTAI (4)· patent assignee history
2013–2014Patents assigned to CHENNUPATY SRINIVAS (4)· patent assignee history
2014–2018Patents assigned to KRASNOV VLAD (7)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP1192010–2021
GUERON SHAYself432011–2018
KRASNOV VLAD72014–2018
ANATI ITTAI42012–2016
CHENNUPATY SRINIVAS42013–2014
Locations
LocationPatentsSpan
Haifa, IL1212010–2021