LexDanaLexDanabeta
Inventor

Anirban Rahut

Inventor
Santa Clara, CA, US

Overview

22→
Patents
2004–2020
Patent span
Physics
Primary field (CPC G)

Patents· 22 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing92%
H10DInorganic electric semiconductor devices8%
PatentTitleYear
10,698,777High availability scheduler for scheduling map-reduce searches based on a leader state202010,133,806Search result replication in a search head cluster20189,983,954High availability scheduler for scheduling searches of time stamped events20189,256,501'High availability scheduler for scheduling map-reduce searches'20169,047,246'High availability scheduler'20158,146,041'Latch based optimization during implementation of circuit designs for programmable logic devices'20128,015,535'Run-time efficient methods for routing large multi-fanout nets'20118,010,923'Latch based optimization during implementation of circuit designs for programmable logic devices'20117,904,860'Method and apparatus for selecting programmable interconnects to reduce clock skew'20117,797,665'Patterns for routing nets in a programmable logic device'20107,735,039'Methods of estimating net delays in tile-based PLD architectures'20107,725,868'Method and apparatus for facilitating signal routing within a programmable logic device'20107,620,923'Run-time efficient methods for routing large multi-fanout nets'20097,430,728'Method and apparatus for selecting programmable interconnects to reduce clock skew'20087,424,697'Assigning inputs of look-up tables to improve a design implementation in a programmable logic device'20087,389,485'Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures'20087,376,926'Run-time efficient methods for routing large multi-fanout nets'20087,306,977'Method and apparatus for facilitating signal routing within a programmable logic device'20077,076,758'Using router feedback for placement improvements for logic design'20067,051,312'Upper-bound calculation for placed circuit design performance'20066,952,813'Method and apparatus for selecting programmable interconnects to reduce clock skew'20056,766,504'Interconnect routing using logic levels'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2012Patents assigned to XILINX INC (17)· patent assignee history
2004–2010Based in San Jose, CA, US· patent location history
2008–2010Based in Sunnyvale, CA, US· patent location history
2009–2020Based in Santa Clara, CA, US· patent location history
2012Patents assigned to CHAUDHARY KAMAL (1)· patent assignee history
2012Patents assigned to KRISHNAMURTHY SRIDHAR (1)· patent assignee history
2012Patents assigned to PHILOFSKY BRIAN D (1)· patent assignee history
2015–2020Patents assigned to SPLUNK INC (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
XILINX INC172004–2012
SPLUNK INC52015–2020
CHAUDHARY KAMAL12012
KRISHNAMURTHY SRIDHAR12012
PHILOFSKY BRIAN D12012
Locations
LocationPatentsSpan
Santa Clara, California, US112009–2020
San Jose, California, US62004–2010
Sunnyvale, California, US52008–2010