Inventor
Manish Shah
Inventor
Austin, TX, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing71%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
G06NComputing arrangements based on specific computational models3%
G11CStatic stores3%
G06KGraphical data reading2%
G06VImage or video recognition or understanding2%
H01RElectrically-conductive connections2%
H02JElectric power networks2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H04BTransmission2%
PatentTitleYear
11,126,577Distributed fairness protocol for interconnect networks202111,099,849Method for reducing fetch cycles for return-type instructions202111,055,141Quiesce reconfigurable data processor202110,860,326Multi-threaded instruction buffer design202010,831,675Adaptive tablewalk translation storage buffer predictor202010,831,507Configuration load of a reconfigurable data processor202010,747,540Hybrid lookahead branch target cache202010,728,769Multi-stage object detection and categorization of antenna mount locations202010,698,853Virtualization of a reconfigurable data processor202010,579,107Reversible connector orientation detection circuitry202010,474,601Distributed fairness protocol for interconnect networks201910,430,342Optimizing thread selection at fetch, select, and commit stages of processor core pipeline201910,346,173Multi-threaded instruction buffer design201910,338,928Utilizing a stack head register with a call return stack for each instruction fetch201910,318,303Method and apparatus for augmentation and disambiguation of branch history in pipelined branch predictors201910,255,197Adaptive tablewalk translation storage buffer predictor201910,250,059Charging circuit for battery-powered device201910,198,260Processing instruction control transfer instructions201910,001,998Dynamically enabled branch prediction20189,529,594'Miss buffer for a multi-threaded processor'20169,213,551'Return address prediction in multithreaded processors'20159,208,261'Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM)'20159,116,876'Programmable built-in-self tester (BIST) in memory controller'20158,904,156'Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor'20148,886,920'Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage'20148,862,861'Suppressing branch prediction information update by branch instructions in incorrect speculative execution path'20148,595,464'Dynamic sizing of translation lookaside buffer for power reduction'20138,195,921'Method and apparatus for decoding multithreaded instructions of a microprocessor'20128,195,919'Handling multi-cycle integer operations for a multi-threaded processor'20128,099,586'Branch misprediction recovery mechanism for microprocessors'20128,037,250'Arbitrating cache misses in a multithreaded/multi-core processor'20117,996,632'Device for misaligned atomics for a highly-threaded x86 processor'20117,937,556'Minimizing TLB comparison size'20117,747,771'Register access protocol in a multihreaded multi-core processor'20107,685,354'Multiple-core processor with flexible mapping of processor cores to cache banks'20107,571,284'Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor'20097,543,132'Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes'20097,454,590'Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores'20087,434,000'Handling duplicate cache misses in a multithreaded/multi-core processor'20087,383,415'Hardware demapping of TLBs shared by multiple threads'20087,383,403'Concurrent bypass to instruction buffers in a fine grain multithreaded processor'20087,353,445'Cache error handling in a multithreaded/multi-core processor'20087,290,116'Level 2 cache index hashing to avoid hot spots'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2010Patents assigned to SUN MICROSYSTEMS INC (9)· patent assignee history
2007–2021Based in Austin, TX, US· patent location history
2010–2014Patents assigned to ORACLE AMERICA INC (8)· patent assignee history
2012–2019Patents assigned to GOLLA ROBERT T (4)· patent assignee history
2013–2021Patents assigned to ORACLE INT CORP (19)· patent assignee history
2013–2019Patents assigned to SHAH MANISH K (8)· patent assignee history
2015Based in San Diego, CA, US· patent location history
2019–2020Based in Redmond, WA, US· patent location history
2020Based in Hillsborough, NJ, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ORACLE INT CORP | 19 | 2013–2021 |
| SUN MICROSYSTEMS INC | 9 | 2007–2010 |
| ORACLE AMERICA INC | 8 | 2010–2014 |
| SHAH MANISH Kself | 8 | 2013–2019 |
| GOLLA ROBERT T | 4 | 2012–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 39 | 2007–2021 |
| Redmond, Washington, US | 2 | 2019–2020 |
| Hillsborough, New Jersey, US | 1 | 2020 |
| San Diego, California, US | 1 | 2015 |