Inventor

Prashant U. Kenkare

Inventor

Austin, TX, US

Overview

1993–2019

Patent span

Physics

Primary field (CPC G)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores46%

H03KPulse technique19%

G06FElectric digital data processing10%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

G01RMeasuring electric variables3%

H02JElectric power networks3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

G05FSystems for regulating electric or magnetic variables1%

PatentTitleYear

10,446,201Distributed global-bitline keeper/precharge/header circuit for low voltage operation2019 10,003,325System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits2018 9,697,889'Method and apparatus for read assist to achieve robust static random access memory (SRAM)'2017 9,647,453'Dual supply memory'2017 9,460,778'Static random access memory with bitline boost'2016 9,450,578'Integrated clock gater (ICG) using clock cascode complimentary switch logic'2016 9,337,840'Voltage level shifter and systems implementing the same'2016 9,330,751'SRAM wordline driver supply block with multiple modes'2016 9,312,857'Semiconductor circuit'2016 9,203,382'Integrated clock gater (ICG) using clock cascode complimentary switch logic'2015 9,059,687'Flip-flop having shared feedback and method of operation'2015 9,021,194'Memory management unit tag memory'2015 8,975,949'Integrated clock gater (ICG) using clock cascode complimentary switch logic'2015 8,943,292'System and method for memory array access with fast address decoder'2015 8,791,739'Flip-flop having shared feedback and method of operation'2014 8,634,263'Integrated circuit having memory repair information storage and method therefor'2014 8,484,523'Sequential digital circuitry with test scan'2013 8,315,117'Integrated circuit memory having assisted access and method therefor'2012 8,156,357'Voltage-based memory size scaling in a data processing system'2012 8,143,929'Flip-flop having shared feedback and method of operation'2012 8,120,975'Memory having negative voltage write assist circuit and method therefor'2012 8,059,482'Memory using multiple supply voltages'2011 8,031,549'Integrated circuit having boosted array voltage and method therefor'2011 8,009,489'Memory with read cycle write back'2011 8,004,907'SRAM with read and write assist'2011 7,984,229'Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access'2011 7,870,400'System having a memory voltage controller which varies an operating voltage of a memory and method therefor'2011 7,864,617'Memory with reduced power supply voltage for a write operation'2011 7,843,218'Data latch with structural hold'2010 7,675,806'Low voltage memory device and method thereof'2010 7,671,629'Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains'2010 7,630,272'Multiple port memory with prioritized world line driver and method thereof'2009 7,623,404'Memory device having concurrent write and read cycles and method thereof'2009 7,573,762'One time programmable element system in an integrated circuit'2009 7,548,102'Data latch with minimal setup time and launch delay'2009 7,545,702'Memory pipelining in an integrated circuit memory device using shared word lines'2009 7,542,369'Integrated circuit having a memory with low voltage read/write operation'2009 7,525,867'Storage circuit and method therefor'2009 7,492,627'Memory with increased write margin bitcells'2009 7,489,540'Bitcell with variable-conductance transfer gate and method thereof'2009 7,369,452'Programmable cell'2008 7,365,587'Contention-free keeper circuit and a method for contention elimination'2008 7,362,134'Circuit and method for latch bypass'2008 7,349,266'Memory device with a data hold latch'2008 7,295,487'Storage circuit and method therefor'2007 7,292,495'Integrated circuit having a memory with low voltage read/write operation'2007 7,242,626'Method and apparatus for low voltage write in a static random access memory'2007 7,200,020'Storage element with clear operation and method thereof'2007 7,193,924'Dual-port static random access memory having improved cell stability and write margin'2007 7,161,827'SRAM having improved cell stability and method therefor'2007 5,422,300'Method for forming electrical isolation in an integrated circuit'1995 5,369,052'Method of forming dual field oxide isolation'1994 5,236,862'Method of forming oxide isolation'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2019Based in Austin, TX, US· patent location history

2007–2015Patents assigned to FREESCALE SEMICONDUCTOR INC (39)· patent assignee history

2009Based in Autin, TX, US· patent location history

2011–2015Patents assigned to KENKARE PRASHANT U (13)· patent assignee history

2011–2014Patents assigned to RUSSELL ANDREW C (4)· patent assignee history

2012–2015Patents assigned to RAMARAJU RAVINDRARAJ (6)· patent assignee history

2015–2019Patents assigned to SAMSUNG ELECTRONICS CO LTD (11)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FREESCALE SEMICONDUCTOR INC	39	2007–2015
KENKARE PRASHANT Uself	13	2011–2015
SAMSUNG ELECTRONICS CO LTD	11	2015–2019
RAMARAJU RAVINDRARAJ	6	2012–2015
RUSSELL ANDREW C	4	2011–2014

Locations

Location	Patents	Span
Austin, Texas, US	52	1993–2019
Autin, Texas, US	1	2009