Inventor
Stephen M. Gates
Inventor
Ossining, NY, US
Overview
Patents· 126 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
Y10TTechnical subjects covered by former us classification12%
H10DInorganic electric semiconductor devices9%
H01LSemiconductor devices6%
B82YSpecific uses or applications of nanostructures3%
H10BElectronic memory devices3%
C23CCoating metallic material3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H01FMagnets1%
PatentTitleYear
10,651,252Vertically integrated active matrix backplane20209,984,940Selective and conformal passivation layer for 3D high-mobility channel devices20189,960,117Air gap semiconductor structure with selective cap bilayer20189,905,667'Lateral bipolar transistor'20189,799,552'Low resistance metal contacts to interconnects'20179,786,550'Low resistance metal contacts to interconnects'20179,784,917'Low-loss large-grain optical waveguide for interconnecting components integrated on a glass substrate'20179,711,455'Method of forming an air gap semiconductor structure with selective cap bilayer'20179,653,567'Lateral bipolar transistor'20179,472,710'Low-loss large-grain optical waveguide for interconnecting components integrated on a glass substrate'20169,425,298'Lateral bipolar transistor'20169,349,687'Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect'20169,318,415'Beol structures incorporating active devices and mechanical strength'20169,305,836'Air gap semiconductor structure with selective cap bilayer'20169,275,936'BEOL structures incorporating active devices and mechanical strength'20169,219,037'Low k porous SiCOH dielectric and integration with post film formation treatment'20159,111,761'Multi component dielectric layer'20159,070,686'Wiring switch designs based on a field effect device for reconfigurable interconnect paths'20159,059,679'Tunable interconnect structures, and integrated circuit containing the same'20159,018,089'Multiple step anneal method and semiconductor formed by multiple step anneal'20158,952,488'Low cost anti-fuse structure'20158,952,486'Electrical fuse and method of making the same'20158,860,095'Interconnect wiring switches and integrated circuits including the same'20148,759,976'Structure with sub-lithographic random conductors as a physical unclonable function'20148,753,927'Low cost anti-fuse structure and method to make same'20148,658,488'Method for forming semiconductor chip with graphene based devices in an interconnect structure of the chip'20148,637,957'Low cost anti-fuse structure'20148,624,323'BEOL structures incorporating active devices and mechanical strength'20148,618,183'Materials containing voids with void size controlled on the nanometer scale'20138,525,169'Reliable physical unclonable function for device authentication'20138,491,987'Selectively coated self-aligned mask'20138,440,999'Semiconductor chip with graphene based devices in an interconnect structure of the chip'20138,386,859'On-chip non-volatile storage of a test-time profile for efficiency and performance control'20138,357,608'Multi component dielectric layer'20138,276,018'Non-volatile memory based reliability and availability mechanisms for a computing device'20128,268,411'Materials containing voids with void size controlled on the nanometer scale'20128,101,236'Method of fabricating a SiCOH dielectric material with improved toughness and improved Si-C bonding'20128,097,932'Ultra low κ plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality'20127,955,968'Pseudo hybrid structure for low K interconnect integration'20117,948,051'Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same'20117,948,083'Reliable BEOL integration process with direct CMP of porous SiCOH dielectric'20117,915,180'SiCOH film preparation using precursors with built-in porogen functionality'20117,892,648'SiCOH dielectric material with improved toughness and improved Si-C bonding'20117,863,749'Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same'20117,847,402'BEOL interconnect structures with improved resistance to stress'20107,811,926'Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics'20107,726,008'Method of forming a magnetic-field sensor having magnetic nanoparticles'20107,674,521'Materials containing voids with void size controlled on the nanometer scale'20107,615,482'Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength'20097,521,377'SiCOH film preparation using precursors with built-in porogen functionality'20097,517,790'Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification'20097,491,658'Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality'20097,485,341'Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same'20097,485,582'Hardmask for improved reliability of silicon based dielectrics'20097,479,306'SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same'20097,439,174'Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics'20087,378,350'Formation of low resistance via contacts in interconnect structures'20087,371,461'Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics'20087,357,977'Ultralow dielectric constant layer with controlled biaxial stress'20087,335,980'Hardmask for reliability of silicon based dielectrics'20087,312,524'Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made'20077,288,292'Ultra low k (ULK) SiCOH film and method'20077,282,458'Low K and ultra low K SiCOH dielectric films and methods to form the same'20077,256,146'Method of forming a ceramic diffusion barrier layer'20077,253,105'Reliable BEOL integration process with direct CMP of porous SiCOH dielectric'20077,252,875'Diffusion barrier with low dielectric constant and semiconductor device containing same'20077,135,398'Reliable low-k interconnect structure with hybrid dielectric'20067,088,003'Structures and methods for integration of ultralow-k dielectrics with improved reliability'20067,049,247'Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made'20067,045,453'Very low effective dielectric constant interconnect structures and methods for fabricating the same'20067,030,468'Low k and ultra low k SiCOH dielectric films and methods to form the same'20067,023,093'Very low effective dielectric constant interconnect Structures and methods for fabricating the same'20066,989,575'Formation of arrays of microelectronic elements'20066,958,526'Electronic structures with reduced capacitance'20056,943,451'Semiconductor devices containing a discontinuous cap layer and methods for forming same'20056,939,797'Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof'20056,940,173'Interconnect structures incorporating low-k dielectric barrier films'20056,929,982'Patterning layers comprised of spin-on ceramic films'20056,917,108'Reliable low-k interconnect structure with hybrid dielectric'20056,911,400'Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same'20056,897,650'Magnetic-field sensor device'20056,831,366'Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer'20046,803,660'Patterning layers comprised of spin-on ceramic films'20046,784,485'Diffusion barrier layer and semiconductor device containing same'20046,780,499'Ordered two-phase dielectric film, and semiconductor device containing the same'20046,756,324'Low temperature processes for making electronic device structures'20046,737,107'Nonoparticles formed with rigid connector compounds'20046,737,727'Electronic structures with reduced capacitance'20046,737,747'Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof'20046,734,096'Fine-pitch device lithography using a sacrificial hardmask'20046,726,996'Laminated diffusion barrier'20046,724,069'Spin-on cap layer, and semiconductor device containing same'20046,716,742'Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics'20046,710,450'Interconnect structure with precise conductor resistance and method to form same'20046,677,680'Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials'20046,673,401'Nanoparticle structures utilizing synthetic DNA lattices'20046,657,305'Semiconductor recessed mask interconnect technology'20036,641,899'Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same'20036,620,659'Merged logic and memory combining thin film and bulk Si transistors'20036,617,690'Interconnect structures containing stress adjustment cap layer'20036,603,204'Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics'20036,599,623'Nanoparticles formed with rigid connector compounds'20036,562,634'Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same'20036,548,901'Cu/low-k BEOL with nonconcurrent hybrid dielectric interface'20036,537,908'Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask'20036,479,110'Multiphase low dielectric constant material and method of deposition'20026,440,560'Nanoparticles formed with rigid connector compounds'20026,437,443'Multiphase low dielectric constant material and method of deposition'20026,391,658'Formation of arrays of microelectronic elements'20026,351,023'Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same'20026,312,793'Multiphase low dielectric constant material'20016,285,050'Decoupling capacitor structure distributed above an integrated circuit and method for making same'20016,271,542'Merged logic and memory combining thin film and bulk Si transistors'20016,265,021'Nanoparticle structures utilizing synthetic DNA lattices'20016,242,770'Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same'20016,203,613'Atomic layer deposition with nitrate containing precursors'20016,180,444'Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same'20016,162,532'Magnetic storage medium formed of nanoparticles'20005,830,538'Method to form a polycrystalline film on a substrate'19985,799,231'Variable index distributed mirror'19985,796,121'Thin film transistors fabricated on plastic substrates'19985,667,586'Method for forming a single crystal semiconductor on a substrate'19975,634,224'Inflatable cushioning device with self opening intake valve'19975,593,249'Diverless flowline connection system'19975,563,428'Layered structure of a substrate, a dielectric layer and a single crystal layer'19964,794,863'Motive structure for transporting workpieces'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2020Patents assigned to IBM (118)· patent assignee history
1989–2020Based in Ossining, NY, US· patent location history
1997Based in Ontario, CA· patent location history
1997Based in Gooseberry Hill, AU· patent location history
2012–2015Patents assigned to GATES STEPHEN M (17)· patent assignee history
2012–2015Patents assigned to GRILL ALFRED (7)· patent assignee history
2012–2015Patents assigned to EDELSTEIN DANIEL C (5)· patent assignee history
2012–2013Patents assigned to NEUMAYER DEBORAH A (4)· patent assignee history
2015Based in Yorktown Heights, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 118 | 1989–2020 |
| GATES STEPHEN Mself | 17 | 2012–2015 |
| GRILL ALFRED | 7 | 2012–2015 |
| EDELSTEIN DANIEL C | 5 | 2012–2015 |
| NEUMAYER DEBORAH A | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ossining, New York, US | 123 | 1989–2020 |
| Yorktown Heights, New York, US | 1 | 2015 |
| Ontario, CA | 1 | 1997 |
| Gooseberry Hill, AU | 1 | 1997 |