Inventor

Renato C. Padilla

Inventor

Folsom, CA, US

Overview

43→

Patents

2016–2021

Patent span

Physics

Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores45%

G06FElectric digital data processing43%

G01RMeasuring electric variables5%

H01LSemiconductor devices3%

H10BElectronic memory devices3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

PatentTitleYear

11,126,495Dynamic error handling in a memory system2021 11,120,885Using a status indicator in a memory sub-system to detect an event2021 11,042,306Memory management2021 11,024,394Implementing sticky read using error control success rate associated with a memory sub-system2021 11,023,177Temperature correction in memory sub-systems2021 10,998,034Temperature informed memory refresh2021 10,949,344Garbage collection2021 10,942,796Identifying asynchronous power loss2021 10,936,416Redundant array of independent NAND for a three-dimensional memory array2021 10,915,395Read retry with targeted auto read calibrate2021 10,877,679Partially written block treatment2020 10,854,305Using a status indicator in a memory sub-system to detect an event2020 10,796,745Temperature informed memory refresh2020 10,770,156Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses2020 10,719,271Temperature correction in memory sub-systems2020 10,691,377Adjusting scan event thresholds to mitigate memory errors2020 10,685,725Performing an operation on a memory cell of a memory system at a frequency based on temperature2020 10,672,452Temperature informed memory refresh2020 10,665,307Memory devices configured to perform leak checks2020 10,658,047Implementing sticky read using error control success rate associated with a memory sub-system2020 10,606,698Mitigating an undetectable error when retrieving critical data during error handling2020 10,593,412Using a status indicator in a memory sub-system to detect an event2020 10,579,307Correcting power loss in NAND memory devices2020 10,529,433Offset memory component automatic calibration (AUTOCAL) error recovery for a memory sub-system2020 10,510,422Memory devices with read level calibration2019 10,452,282Memory management2019 10,430,116Correcting power loss in NAND memory devices2019 10,430,262Identifying asynchronous power loss2019 10,423,350Partially written block treatment2019 10,403,378Performing an operation on a memory cell of a memory system at a frequency based on temperature2019 10,380,018Garbage collection2019 10,366,767Memory devices configured to perform leak checks2019 10,359,963Partially written block treatment2019 10,359,933Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods2019 10,340,016Methods of error-based read disturb mitigation and memory devices utilizing the same2019 10,331,553Garbage collection2019 10,325,668Operation of mixed mode blocks2019 10,318,378Redundant array of independent NAND for a three-dimensional memory array2019 10,303,535Identifying asynchronous power loss2019 10,199,111Memory devices with read level calibration2019 9,921,898'Identifying asynchronous power loss'2018 9,761,322'Program operations with embedded leak checks'2017 9,281,078'Program operations with embedded leak checks'2016

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2016–2021Patents assigned to MICRON TECHNOLOGY INC (41)· patent assignee history

2016–2021Based in Boise, ID, US· patent location history

2019–2021Based in Folsom, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	41	2016–2021

Locations

Location	Patents	Span
Folsom, California, US	32	2019–2021
Boise, ID, US	11	2016–2021