Inventor

CHIN-CHOU LIU

Inventor

TW

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 41 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%

H01LSemiconductor devices22%

G06FElectric digital data processing17%

H10DInorganic electric semiconductor devices16%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%

G11CStatic stores3%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%

Y02PClimate change mitigation technologies in the production or processing of goods3%

G01RMeasuring electric variables1%

H01FMagnets1%

PatentTitleYear

12,532,731Interconnect structure2026 12,450,412Method and system for determining equivalence of design rule manual data and design rule checking data2025 12,424,515SOIC chip architecture2025 12,315,862Integrated circuit device with improved layout2025 12,277,379Method and system for generating layout diagram including wiring arrangement2025 12,261,199Thermoelectric cooling of semiconductor devices2025 12,223,252Through-silicon via in integrated circuit packaging2025 12,216,981System and method for generating layout diagram including wiring arrangement2025 12,154,842Heat dissipation structures for three-dimensional system on integrated chip structure2024 12,079,561Cell region including portion of conductor of another cell region and semiconductor device include the same2024 12,062,641Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same2024 12,039,244Hybrid node chiplet stacking design2024 12,027,513Layout design methodology for stacked devices2024 12,009,260Method and system of forming integrated circuit2024 12,002,776Interconnect structure and method for forming the same2024 11,983,475Method for manufacturing a cell having pins and semiconductor device based on same2024 11,935,894Integrated circuit device with improved layout2024 11,923,302Semiconductor device and method of manufacture2024 11,923,2713D IC power grid2024 11,842,133Method and system for determining equivalence of design rule manual data and design rule checking data2023 11,790,151System for generating layout diagram including wiring arrangement2023 11,775,727Method for generating layout diagram including wiring arrangement2023 11,756,951Layout design methodology for stacked devices2023 11,749,584Heat dissipation structures2023 11,727,188Semiconductor device including protruding conductor cell regions2023 11,715,668Integrated antenna on interposer substrate2023 11,694,973Electromagnetic shielding metal-insulator-metal capacitor structure2023 11,658,157Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same2023 11,586,797Through-silicon vias in integrated circuit packaging2023 11,585,831Test probing structure2023 11,574,107Method for manufacturing a cell having pins and semiconductor device based on same2023 11,545,298Method of forming entangled inductor structures2023 11,532,580Interconnect structure, semiconductor structure including interconnect structure and method for forming the same2022 11,495,619Integrated circuit device with improved layout2022 11,410,929Semiconductor device and method of manufacture2022 11,397,842Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same2022 11,387,177Package structure and method for forming the same2022 11,367,695Interposer with capacitors2022 11,222,884Layout design methodology for stacked devices2022 11,211,333Through silicon via optimization for three-dimensional integrated circuits2021 11,138,360Semiconductor device with filler cell region, method of generating layout diagram and system for same2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (41)· patent assignee history

2021–2026Based in TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	41	2021–2026

Locations

Location	Patents	Span
TW	41	2021–2026