Inventor
Vinod Ramadurai
Inventor
South Burlington, VT, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores69%
H03KPulse technique15%
G06FElectric digital data processing8%
G01RMeasuring electric variables4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
9,047,930'Single-ended low-swing power-savings mechanism with process compensation'20158,363,453'Static random access memory (SRAM) write assist circuit with leakage suppression and level control'20138,279,687'Single supply sub VDD bit-line precharge SRAM and method for level shifting'20128,120,987'Structure and method for decoding read data-bus with column-steering redundancy'20127,890,907'Computer program product for designing memory circuits having single-ended memory cells with improved read stability'20117,795,928'Circuit for matching semiconductor device behavior'20107,791,977'Design structure for low overhead switched header power savings apparatus'20107,793,235'Method and circuit for matching semiconductor device behavior'20107,788,443'Transparent multi-hit correction in associative memories'20107,733,689'Methods of operating and designing memory circuits having single-ended memory cells with improved read stability'20107,715,222'Configurable SRAM system and method'20107,668,682'Method and circuit for detecting and compensating for a degradation of a semiconductor device'20107,643,357'System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture'20107,602,635'Structure for a configurable SRAM system and method'20097,489,582'Low overhead switched header power savings apparatus'20097,480,810'Voltage droop dynamic recovery'20097,450,413'Configurable SRAM system and method'20087,420,836'Single-ended memory cell with improved read stability and memory using the cell'20087,400,546'Low overhead switched header power savings apparatus'20087,382,165'Method for matching semiconductor device behavior'20087,352,252'Circuit and method to measure threshold voltage distributions in SRAM devices'20087,333,379'Balanced sense amplifier circuits with adjustable transistor body bias'20087,042,776'Method and circuit for dynamic read margin control of a memory array'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2015Patents assigned to IBM (23)· patent assignee history
2006–2015Based in South Burlington, VT, US· patent location history
2008Based in Burlington, VT, US· patent location history
2012–2013Patents assigned to RAMADURAI VINOD (3)· patent assignee history
2012–2013Patents assigned to PILO HAROLD (2)· patent assignee history
2012Patents assigned to ADAMS CHAD A (1)· patent assignee history
2012Based in Austin, TX, US· patent location history
2013Patents assigned to ARSOVSKI IGOR (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 23 | 2006–2015 |
| RAMADURAI VINODself | 3 | 2012–2013 |
| PILO HAROLD | 2 | 2012–2013 |
| ADAMS CHAD A | 1 | 2012 |
| ARSOVSKI IGOR | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 21 | 2006–2015 |
| Austin, Texas, US | 1 | 2012 |
| Burlington, VT, US | 1 | 2008 |