Inventor
Takeki Osanai
Inventor
Austin, TX, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing83%
G01RMeasuring electric variables6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
PatentTitleYear
7,769,985'Load address dependency mechanism system and method in a high frequency, low power processor system'20107,730,290'Systems for executing load instructions that achieve sequential load consistency'20107,725,686'Systems and methods for processing buffer data retirement conditions'20107,689,776'Method and system for efficient cache locking mechanism'20107,631,149'Systems and methods for providing fixed-latency data access in a memory system having multi-level caches'20097,607,059'Systems and methods for improved scan testing fault coverage'20097,464,242'Method of load/store dependencies detection with dynamically changing address length'20087,376,816'Method and systems for executing load instructions that achieve sequential load consistency'20087,363,468'Load address dependency mechanism system and method in a high frequency, low power processor system'20087,346,624'Systems and methods for processing buffer data retirement conditions'20087,302,527'Systems and methods for executing load instructions that avoid order violations'20077,302,530'Method of updating cache state information where stores only read the cache state information upon entering the queue'20077,240,183'System and method for detecting instruction dependencies in multiple phases'20076,389,527'Microprocessor allowing simultaneous instruction execution and DMA transfer'20026,360,298'Load/store instruction control circuit of microprocessor and load/store instruction control method'20026,327,665'Processor with power consumption limiting function'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2010Patents assigned to TOSHIBA KK (8)· patent assignee history
2001Based in Tokyo, JP· patent location history
2002Based in Ebina, JP· patent location history
2007–2010Patents assigned to IBM (10)· patent assignee history
2007–2010Based in Austin, TX, US· patent location history
2007–2010Based in Kanagawa, JP· patent location history
2010Patents assigned to HABUSHIKI KAISHA TOSHIBA (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 10 | 2007–2010 |
| TOSHIBA KK | 8 | 2001–2010 |
| HABUSHIKI KAISHA TOSHIBA | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 8 | 2007–2010 |
| Kanagawa, JP | 5 | 2007–2010 |
| Ebina, JP | 2 | 2002 |
| Tokyo, JP | 1 | 2001 |