Inventor
Michael J. Grubisich
Inventor
San Jose, CA, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G06FElectric digital data processing7%
H03KPulse technique7%
G01RMeasuring electric variables3%
H01LSemiconductor devices3%
PatentTitleYear
9,209,137'Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits'20158,785,246'Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits'20146,668,346'Digital process monitor'20035,698,459'Fabrication of bipolar transistors using selective doping to improve performance characteristics'19975,589,409'Fabrication of bipolar transistors with improved output current-voltage characteristics'19965,580,798'Method of fabricating bipolar transistor having a guard ring'19965,581,115'Bipolar transistors using isolated selective doping to improve performance characteristics'19965,548,158'Structure of bipolar transistors with improved output current-voltage characteristics'19965,543,653'Bipolar and BiCMOS structures'19965,508,552'Transistors with multiple emitters, and transistors with substantially square base emitter junctions'19965,455,189'Method of forming BICMOS structures'19955,451,546'Masking method used in salicide process for improved yield by preventing damage to oxide spacers'19955,389,553'Methods for fabrication of transistors'19955,387,813'Transistors with emitters having at least three sides'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–1997Patents assigned to NAT SEMICONDUCTOR CORP (11)· patent assignee history
1995–2015Based in San Jose, CA, US· patent location history
2014Patents assigned to ATTARAN SEYED (1)· patent assignee history
2014Patents assigned to GRUBISICH MICHAEL J (1)· patent assignee history
2014Patents assigned to MEDURI VIJAY (1)· patent assignee history
2015Patents assigned to AVAGO TECHNOLOGIES GENERAL IP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 11 | 1995–1997 |
| ATTARAN SEYED | 1 | 2014 |
| AVAGO TECHNOLOGIES GENERAL IP | 1 | 2015 |
| GRUBISICH MICHAEL Jself | 1 | 2014 |
| MEDURI VIJAY | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 14 | 1995–2015 |