Inventor
Howard H. Smith
Inventor
Beacon, NY, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing84%
G01RMeasuring electric variables12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
10,467,372Implementing automated identification of optimal sense point and sector locations in various on-chip linear voltage regulator designs20199,607,118'Evaluating on-chip voltage regulation'20179,582,622'Evaluating on-chip voltage regulation'20177,971,171'Method and system for electromigration analysis on signal wiring'20117,844,435'Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques'20107,346,877'Decoupling capacitance analysis method'20087,319,946'Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques'20087,269,806'Decoupling capacitance analysis method'20077,093,206'Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures'20067,086,026'Decoupling capacitance analysis method'20067,006,931'System and method for efficient analysis of transmission lines'20066,963,204'Method to include delta-I noise on chip using lossy transmission line representation for the power mesh'20056,618,843'Method for evaluating decoupling capacitor placement for VLSI chips'20036,618,844'Method for evaluating decoupling capacitor placement for VLSI chips'20036,546,529'Method for performing coupling analysis'20036,460,169'Routing program method for positioning unit pins in a hierarchically designed VLSI chip'20026,418,401'Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation'20026,415,428'Minimal length method for positioning unit pins in a hierarchically designed VLSI chip'20026,374,394'Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip'20026,342,823'System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation'20026,333,680'Method and system for characterizing coupling capacitance between integrated circuit interconnects'20016,323,050'Method for evaluating decoupling capacitor placement for VLSI chips'20016,279,142'Method of on-chip interconnect design'20016,028,989'Calculating crosstalk voltage from IC craftsman routing data'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2019Patents assigned to IBM (24)· patent assignee history
2000–2019Based in Beacon, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 24 | 2000–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beacon, New York, US | 24 | 2000–2019 |