Inventor
Kai Chirca
Inventor
Dallas, TX, US
Overview
Patents· 59 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing54%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%
H04LTransmission of digital information, e.g. telegraphic communication12%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications7%
H03MCoding5%
H03HImpedance networks, e.g. resonant circuits3%
G06NComputing arrangements based on specific computational models2%
PatentTitleYear
11,119,776Cache management operations using streaming engine202111,106,463System and method for addressing data in memory202111,099,993Multi-processor bridge with cache allocate awareness202111,099,994Virtual network pre-arbitration for deadlock avoidance and enhanced performance202111,086,967Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA)202111,086,778Multicore shared cache operation engine202111,074,190Slot/sub-slot prefetch architecture for multiple memory requestors202111,055,095Nested loop control202111,036,648Highly integrated scalable, flexible DSP megamodule architecture202110,990,398Mechanism for interrupting and resuming execution on an unprotected pipeline processor202110,990,529Multi-power-domain bridge with prefetch and write merging202110,963,255Implied fence on stream open202110,817,587Reconfigurable matrix multiplier system and method202010,802,974Virtual network pre-arbitration for deadlock avoidance and enhanced performance202010,795,844Multicore bus architecture with non-blocking high performance transaction credit system202010,747,636Streaming engine with deferred exception reporting202010,732,945Nested loop control202010,606,596Cache preload operations using streaming engine202010,599,433Cache management operations using streaming engine202010,560,428Flexible hybrid firewall architecture202010,394,718Slot/sub-slot prefetch architecture for multiple memory requestors201910,311,007Multicore bus architecture with non-blocking high performance transaction credit system201910,162,641Highly integrated scalable, flexible DSP megamodule architecture201810,061,675Streaming engine with deferred exception reporting201810,037,439Secure master and secure guest endpoint security firewall20189,904,645'Multicore bus architecture with non-blocking high performance transaction credit system'20189,898,415'Slot/sub-slot prefetch architecture for multiple memory requestors'20189,652,404'Multicore, multibank, fully concurrent coherence controller'20179,606,803'Highly integrated scalable, flexible DSP megamodule architecture'20179,557,936'Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors'20179,489,314'Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC'20169,465,767'Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect'20169,465,742'Synchronizing barrier support with zero performance impact'20169,465,741'Multi processor multi domain conversion bridge with out of order return buffering'20169,448,767'Three-term predictive adder and/or subtracter'20169,424,193'Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems'20169,372,796'Optimum cache access scheme for multi endpoint atomic access in a multicore system'20169,372,808'Deadlock-avoiding coherent system on chip interconnect'20169,372,799'Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion'20169,304,925'Distributed data return buffer for coherence system with speculative address support'20169,304,954'Multi processor bridge with mixed Endian mode support'20169,298,665'Multicore, multibank, fully concurrent coherence controller'20169,239,798'Prefetcher with arbitrary downstream prefetch cancelation'20169,213,656'Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems'20159,208,120'Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect'20159,152,586'Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion'20159,129,071'Coherence controller slot architecture allowing zero latency write commit'20159,075,928'Hazard detection and elimination for coherent endpoint allowing out-of-order execution'20158,977,819'Prefetch stream filter with FIFO allocation and stream direction prediction'20158,880,847'Multistream prefetch buffer'20148,732,551'Memory controller with automatic error detection and correction'20148,732,370'Multilayer arbitration for access to multiple destinations'20148,713,086'Three-term predictive adder and/or subtracter'20148,706,969'Variable line size prefetcher for multiple memory requestors'20148,706,940'High fairness variable priority arbitration method'20148,601,221'Speculation-aware memory controller arbiter'20138,473,689'Predictive sequential prefetching for data caching'20138,117,422'Fast address translation for linear and circular modes'20127,349,938'Arithmetic circuit with balanced logic levels for low-power operation'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2021Based in Richardson, TX, US· patent location history
2012–2021Patents assigned to TEXAS INSTRUMENTS INC (57)· patent assignee history
2012–2018Patents assigned to CHIRCA KAI (12)· patent assignee history
2012–2016Patents assigned to ANDERSON TIMOTHY D (10)· patent assignee history
2013–2018Patents assigned to ZBICIAK JOSEPH R M (4)· patent assignee history
2014–2016Patents assigned to MENON AMITABH (3)· patent assignee history
2015–2021Based in Dallas, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 57 | 2012–2021 |
| CHIRCA KAIself | 12 | 2012–2018 |
| ANDERSON TIMOTHY D | 10 | 2012–2016 |
| ZBICIAK JOSEPH R M | 4 | 2013–2018 |
| MENON AMITABH | 3 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dallas, Texas, US | 43 | 2015–2021 |
| Richardson, Texas, US | 16 | 2008–2021 |