Inventor

Walter Michael Pitio

Inventor
Morganville, NJ, US

Overview

26→
Patents
1993–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication28%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes14%
H04JMultiplex communication14%
G06FElectric digital data processing12%
H03MCoding7%
G01DMeasuring not specially adapted for a specific variable5%
G06TImage data processing or generation, in general5%
H01HElectric switches5%
H04QSelecting5%
G02BOptical elements, systems or apparatus2%
PatentTitleYear
10,771,536Coordinated processing of data by networked computing resources202010,623,478Coordinated processing of data by networked computing resources202010,284,462Verification of data processes in a network of computing resources201910,055,865System and method for presenting dynamic visualizations201810,057,333Coordinated processing of data by networked computing resources20189,979,589Coordinated processing of data by networked computing resources20189,959,572Coordinated processing of data by networked computing resources20189,922,436'System and method for presenting dynamic visualizations'20188,958,192'Circuit breaker'20158,203,816'Circuit breaker'20127,349,411'Economically expansible switching network'20087,269,130'Redundant add/drop multiplexor'20077,225,219'Distributed caching architecture for computer networks'20077,161,965'Add/drop multiplexor with aggregate serializer/deserializers'20077,145,922'Composite add/drop multiplexor with crisscross loop back'20067,110,424'Bi-directional serializer/deserializer with discretionary loop-back'20066,973,048'Composite add/drop multiplexor'20056,876,227'Simplifying the layout of printed circuit boards'20056,671,833'Forward error correction and framing protocol'20036,593,863'Serializer'20036,556,152'Deserializer'20035,983,278'Low-loss, fair bandwidth allocation flow control in a packet switch'19995,834,980'Method and apparatus for supplying synchronization signals securing as clock signals with defined phase relationships'19985,524,154'Hybrid architecture for an optical switching fabric implemented with 1.times.2 switching devices'19965,317,658'Apparatus and method for providing a polarization independent optical switch'19945,177,737'Multipurpose bus system'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–1994Patents assigned to AT & T BELL LAB (2)· patent assignee history
1993–1999Based in Old Bridge, NJ, US· patent location history
1998–1999Patents assigned to LUCENT TECHNOLOGIES INC (2)· patent assignee history
2003–2005Patents assigned to PARAMA NETWORKS INC (4)· patent assignee history
2003–2020Based in Morganville, NJ, US· patent location history
2005–2008Patents assigned to BAY MICROSYSTEMS INC (6)· patent assignee history
2018–2020Patents assigned to ROYAL BANK OF CANADA (8)· patent assignee history
2019Based in Moganville, NJ, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ROYAL BANK OF CANADA82018–2020
BAY MICROSYSTEMS INC62005–2008
PARAMA NETWORKS INC42003–2005
AT & T BELL LAB21993–1994
LUCENT TECHNOLOGIES INC21998–1999
Locations
LocationPatentsSpan
Morganville, New Jersey, US202003–2020
Old Bridge, New Jersey, US51993–1999
Moganville, New Jersey, US12019