Inventor
Deva Pattanayak
Inventor
Saratoga, CA, US
Overview
Patents· 58 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices51%
H01LSemiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
A61BDiagnosis3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
H04BTransmission2%
B06BMethods or apparatus for generating or transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency, e.g. for performing mechanical work in general1%
G01HMeasurement of mechanical vibrations or ultrasonic, sonic or infrasonic waves1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
PatentTitleYear
10,546,750System and method for substrate wafer back side and edge cross section seals202010,453,953Structures and methods of fabricating dual gate devices201910,340,377Edge termination for super-junction MOSFETs201910,283,587Modulated super junction power MOSFET devices201910,229,988Adaptive charge balanced edge termination201910,032,901Semiconductor device with trench-like feed-throughs201810,026,835Field boosted metal-oxide-semiconductor field effect transistor20189,887,266'Ultra-low drain-source resistance power MOSFET'20189,887,259'Modulated super junction power MOSFET devices'20189,882,044'Edge termination for super-junction MOSFETs'20189,853,140Adaptive charge balanced MOSFET techniques20179,842,911'Adaptive charge balanced edge termination'20179,831,336Process for forming a short channel trench MOSFET and device formed thereby20179,577,089'Structures and methods of fabricating dual gate devices'20179,508,596'Processes used in fabricating a metal-insulator-semiconductor field effect transistor'20169,443,974'Super junction trench power MOSFET device fabrication'20169,437,424'High mobility power metal-oxide semiconductor field-effect transistors'20169,431,550'Trench polysilicon diode'20169,431,249'Edge termination for super junction MOSFET devices'20169,425,043'High mobility power metal-oxide semiconductor field-effect transistors'20169,425,306'Super junction trench power MOSFET devices'20169,306,056'Semiconductor device with trench-like feed-throughs'20169,230,810'System and method for substrate wafer back side and edge cross section seals'20168,883,580'Trench metal oxide semiconductor with recessed trench material and remote contacts'20148,883,595'Process for forming a short channel trench MOSFET and device formed thereby'20148,409,954'Ultra-low drain-source resistance power MOSFET'20138,368,126'Trench metal oxide semiconductor with recessed trench material and remote contacts'20138,183,629'Stacked trench metal-oxide-semiconductor field effect transistor device'20128,072,013'Trench polysilicon diode'20117,833,863'Method of manufacturing a closed cell trench MOSFET'20107,704,836'Method of fabricating super trench MOSFET including buried source electrode'20107,692,211'Super GTO-based power blocks'20107,612,431'Trench polysilicon diode'20097,557,409'Super trench MOSFET including buried source electrode'20097,544,545'Trench polysilicon diode'20097,361,558'Method of manufacturing a closed cell trench MOSFET'20087,344,945'Method of manufacturing a drain side gate trench metal-oxide-semiconductor field effect transistor'20087,279,743'Closed cell trench metal-oxide-semiconductor field effect transistor'20077,233,043'Triple-diffused trench MOSFET'20077,183,610'Super trench MOSFET including buried source electrode and method of fabricating the same'20077,012,005'Self-aligned differential oxidation in trenches by ion implantation'20066,913,977'Triple-diffused trench MOSFET and method of fabricating the same'20056,906,380'Drain side gate trench metal-oxide-semiconductor field effect transistor'20056,903,412'Trench MIS device with graduated gate oxide layer'20056,875,657'Method of fabricating trench MIS device with graduated gate oxide layer'20056,709,930'Thicker oxide formation at the trench bottom by selective oxide deposition'20046,580,853'Optical high speed communications for a computed tomography x-ray machine'20036,396,613'Optical high speed communications for a computed tomography x-ray machine'20026,245,015'Photosonic diffusion wave-based tumor detector'20015,748,564'Amplified acousto-optical vibration sensor and ultrasonic transducer array'19985,655,276'Method of manufacturing two-dimensional array ultrasonic transducers'19974,980,740'MOS-pilot structure for an insulated gate transistor'19904,963,951'Lateral insulated gate bipolar transistors with improved latch-up immunity'19904,912,541'Monolithically integrated bidirectional lateral semiconductor device with insulated gate control in both directions and method of fabrication'19904,888,627'Monolithically integrated lateral insulated gate semiconductor device'19894,857,983'Monolithically integrated semiconductor device having bidirectional conducting capability and method of fabrication'19894,847,671'Monolithically integrated insulated gate semiconductor device'19894,801,985'Monolithically integrated semiconductor device and process for fabrication'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2002Patents assigned to GEN ELECTRIC (11)· patent assignee history
1989–2001Based in Schenectady, NY, US· patent location history
1997–2003Based in Niskayuna, NY, US· patent location history
2004–2010Patents assigned to SILICONIX INC (9)· patent assignee history
2004–2012Based in Cupertino, CA, US· patent location history
2005–2020Patents assigned to VISHAY SILICONIX (35)· patent assignee history
2007–2020Based in Saratoga, CA, US· patent location history
2011–2018Patents assigned to PATTANAYAK DEVA (13)· patent assignee history
2011–2018Patents assigned to TERRILL KYLE (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VISHAY SILICONIX | 35 | 2005–2020 |
| PATTANAYAK DEVAself | 13 | 2011–2018 |
| GEN ELECTRIC | 11 | 1989–2002 |
| TERRILL KYLE | 10 | 2011–2018 |
| SILICONIX INC | 9 | 2004–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 33 | 2007–2020 |
| Cupertino, California, US | 13 | 2004–2012 |
| Schenectady, New York, US | 8 | 1989–2001 |
| Niskayuna, New York, US | 4 | 1997–2003 |